Simulation Results: rv_timer

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 727.763us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 14.842us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 42.812us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 282.039us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 54.826us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 31.041us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 42.812us 1 1 100.00
rv_timer_csr_aliasing 2.000s 54.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 2367.314us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3536.084us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 3.000s 1223.702us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 3.000s 1223.702us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.000s 9119.601us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 33.324us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 17.654us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.000s 53.097us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.000s 53.097us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 14.842us 1 1 100.00
rv_timer_csr_rw 1.000s 42.812us 1 1 100.00
rv_timer_csr_aliasing 2.000s 54.826us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 29.141us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 14.842us 1 1 100.00
rv_timer_csr_rw 1.000s 42.812us 1 1 100.00
rv_timer_csr_aliasing 2.000s 54.826us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 29.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 636.459us 1 1 100.00
rv_timer_tl_intg_err 1.000s 476.784us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 476.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 60.896us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 259.509us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 16.000s 12577.505us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 104187610491722751845069170448624447582166001653818483417538900359836605005763 84
UVM_FATAL @ 60896054 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x59c45f04) == 0x1
UVM_INFO @ 60896054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 17732018282120398939511595385991354399677990307348864521702103235330550499476 86
UVM_FATAL @ 2367313921 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd827a904) == 0x1
UVM_INFO @ 2367313921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 49450922637466560918112386536375082226564984673680744828197446657404799776983 84
UVM_ERROR @ 259508865 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 259508865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---