Simulation Results

Simulation Results: spi_device/1r1w

07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
85.18 %

code
91.61 %

assert
94.64 %

func
69.30 %

block
98.29 %

line
98.73 %

branch
96.89 %

toggle
81.25 %

FSM
89.58 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	34.000s	2443.146us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	2.000s	61.451us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	4.000s	449.937us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	33.000s	3617.274us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	8.000s	362.790us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	3.000s	71.108us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	4.000s	449.937us	1	1	100.00
	spi_device_csr_aliasing	8.000s	362.790us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	2.000s	11.152us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	3.000s	63.952us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	2.000s	58.837us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	2.000s	1.783us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	2.000s	3.519us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	2.000s	37.761us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	2.000s	37.761us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	17.000s	5466.381us	1	1	100.00
	spi_device_tpm_sts_read	1.000s	30.729us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	35.000s	9387.143us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	6.000s	502.334us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	34.000s	5211.701us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	34.000s	5211.701us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	11.000s	5664.292us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	11.000s	5664.292us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	11.000s	5664.292us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	11.000s	5664.292us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	11.000s	5664.292us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	21.000s	2910.167us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	103.000s	14729.120us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	103.000s	14729.120us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	103.000s	14729.120us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	34.000s	1804.299us	1	1	100.00
	spi_device_read_buffer_direct	6.000s	532.663us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	103.000s	14729.120us	1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	226.000s	53078.487us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	3.000s	49.541us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	3.000s	49.541us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	34.000s	2443.146us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	37.000s	14094.010us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	2.000s	50.571us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	3.000s	15.150us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	1.000s	12.116us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	4.000s	274.205us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	4.000s	274.205us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	61.451us	1	1	100.00
	spi_device_csr_rw	4.000s	449.937us	1	1	100.00
	spi_device_csr_aliasing	8.000s	362.790us	1	1	100.00
	spi_device_same_csr_outstanding	4.000s	358.629us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	61.451us	1	1	100.00
	spi_device_csr_rw	4.000s	449.937us	1	1	100.00
	spi_device_csr_aliasing	8.000s	362.790us	1	1	100.00
	spi_device_same_csr_outstanding	4.000s	358.629us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_sec_cm	3.000s	112.619us	1	1	100.00
	spi_device_tl_intg_err	14.000s	777.435us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	14.000s	777.435us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	171.000s	17694.173us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	spi_device_mem_parity	30580917738876476679519453861532231766063250172339906384681670308945073239234	87	UVM_ERROR @ 1129553 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[96] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_ERROR @ 1129553 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) ERROR: VHPI NOTFOUND Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992] not found within the scope . UVM_ERROR @ 1129553 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	91198352928685649290599633260239613019663345358023224351868094080310875118497	85	UVM_ERROR @ 1201848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd3dfbe [110100111101111110111110] vs 0x0 [0]) UVM_ERROR @ 1202848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe72fda [111001110010111111011010] vs 0x0 [0]) UVM_ERROR @ 1237848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc6113c [110001100001000100111100] vs 0x0 [0]) UVM_ERROR @ 1285848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c5cb [1111100010111001011] vs 0x0 [0]) UVM_ERROR @ 1372848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4b740d [10010110111010000001101] vs 0x0 [0])