Simulation Results: spi_host

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.45 %
  • code
  • 94.98 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 21.000s 1879.065us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 138.074us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 18.140us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 162.391us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 25.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 43.814us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 18.140us 1 1 100.00
spi_host_csr_aliasing 1.000s 25.947us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 26.763us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 21.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 56.862us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 192.897us 1 1 100.00
spi_host_error_cmd 2.000s 32.168us 1 1 100.00
spi_host_event 9.000s 950.261us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 130.817us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 130.817us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 130.817us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 15.000s 743.854us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 33.385us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 130.817us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 130.817us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 21.000s 1879.065us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 21.000s 1879.065us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 26.000s 5029.542us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 299.929us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 44.000s 1463.054us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 14.000s 3091.269us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 192.897us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 22.896us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 20.212us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 94.789us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 94.789us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 138.074us 1 1 100.00
spi_host_csr_rw 1.000s 18.140us 1 1 100.00
spi_host_csr_aliasing 1.000s 25.947us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 33.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 138.074us 1 1 100.00
spi_host_csr_rw 1.000s 18.140us 1 1 100.00
spi_host_csr_aliasing 1.000s 25.947us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 33.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 65.897us 1 1 100.00
spi_host_sec_cm 1.000s 498.662us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 65.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 63.000s 2794.321us 1 1 100.00