Simulation Results

Simulation Results: sram_ctrl/ret

07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.85 %

code
82.56 %

assert
95.60 %

func
94.40 %

block
93.27 %

line
94.25 %

branch
87.70 %

toggle
81.62 %

FSM
66.67 %

Validation stages

V1		100.00%
V2		90.00%
V2S		70.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sram_ctrl_smoke	14.000s	953.641us	1	1	100.00
csr_hw_reset				1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	47.484us	1	1	100.00
csr_rw				1	1	100.00
	sram_ctrl_csr_rw	1.000s	22.537us	1	1	100.00
csr_bit_bash				1	1	100.00
	sram_ctrl_csr_bit_bash	1.000s	52.971us	1	1	100.00
csr_aliasing				1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	32.339us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	104.027us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sram_ctrl_csr_rw	1.000s	22.537us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	32.339us	1	1	100.00
mem_walk				1	1	100.00
	sram_ctrl_mem_walk	8.000s	379.792us	1	1	100.00
mem_partial_access				1	1	100.00
	sram_ctrl_mem_partial_access	3.000s	321.764us	1	1	100.00

18/20 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				1	1	100.00
	sram_ctrl_multiple_keys	677.000s	27589.297us	1	1	100.00
stress_pipeline				1	1	100.00
	sram_ctrl_stress_pipeline	165.000s	31946.229us	1	1	100.00
bijection				1	1	100.00
	sram_ctrl_bijection	49.000s	6048.129us	1	1	100.00
access_during_key_req				1	1	100.00
	sram_ctrl_access_during_key_req	1452.000s	14388.850us	1	1	100.00
lc_escalation				1	1	100.00
	sram_ctrl_lc_escalation	7.000s	496.330us	1	1	100.00
executable				1	1	100.00
	sram_ctrl_executable	520.000s	4376.428us	1	1	100.00
partial_access				2	2	100.00
	sram_ctrl_partial_access	14.000s	2118.599us	1	1	100.00
	sram_ctrl_partial_access_b2b	329.000s	84536.796us	1	1	100.00
max_throughput				1	3	33.33
	sram_ctrl_max_throughput	1.000s	27.257us	0	1	0.00
	sram_ctrl_throughput_w_partial_write	61.000s	423.842us	1	1	100.00
	sram_ctrl_throughput_w_readback	2.000s	92.995us	0	1	0.00
regwen				1	1	100.00
	sram_ctrl_regwen	567.000s	3872.477us	1	1	100.00
ram_cfg				1	1	100.00
	sram_ctrl_ram_cfg	1.000s	47.257us	1	1	100.00
stress_all				1	1	100.00
	sram_ctrl_stress_all	2609.000s	159218.547us	1	1	100.00
alert_test				1	1	100.00
	sram_ctrl_alert_test	2.000s	25.147us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sram_ctrl_tl_errors	3.000s	131.488us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sram_ctrl_tl_errors	3.000s	131.488us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	47.484us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	22.537us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	32.339us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	19.292us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	47.484us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	22.537us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	32.339us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	19.292us	1	1	100.00

V2S

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	890.428us	1	1	100.00
tl_intg_err				1	2	50.00
	sram_ctrl_tl_intg_err	3.000s	856.645us	1	1	100.00
	sram_ctrl_sec_cm	2.000s	14.294us	0	1	0.00
prim_count_check				0	1	0.00
	sram_ctrl_sec_cm	2.000s	14.294us	0	1	0.00
sec_cm_bus_integrity				1	1	100.00
	sram_ctrl_tl_intg_err	3.000s	856.645us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	sram_ctrl_regwen	567.000s	3872.477us	1	1	100.00
sec_cm_readback_config_regwen				1	1	100.00
	sram_ctrl_regwen	567.000s	3872.477us	1	1	100.00
sec_cm_exec_config_regwen				1	1	100.00
	sram_ctrl_csr_rw	1.000s	22.537us	1	1	100.00
sec_cm_exec_config_mubi				1	1	100.00
	sram_ctrl_executable	520.000s	4376.428us	1	1	100.00
sec_cm_exec_intersig_mubi				1	1	100.00
	sram_ctrl_executable	520.000s	4376.428us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	1	100.00
	sram_ctrl_executable	520.000s	4376.428us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				1	1	100.00
	sram_ctrl_lc_escalation	7.000s	496.330us	1	1	100.00
sec_cm_prim_ram_ctrl_mubi				0	1	0.00
	sram_ctrl_mubi_enc_err	2.000s	49.509us	0	1	0.00
sec_cm_mem_integrity				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	890.428us	1	1	100.00
sec_cm_mem_readback				0	1	0.00
	sram_ctrl_readback_err	2.000s	114.984us	0	1	0.00
sec_cm_mem_scramble				1	1	100.00
	sram_ctrl_smoke	14.000s	953.641us	1	1	100.00
sec_cm_addr_scramble				1	1	100.00
	sram_ctrl_smoke	14.000s	953.641us	1	1	100.00
sec_cm_instr_bus_lc_gated				1	1	100.00
	sram_ctrl_executable	520.000s	4376.428us	1	1	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	1	0.00
	sram_ctrl_sec_cm	2.000s	14.294us	0	1	0.00
sec_cm_key_global_esc				1	1	100.00
	sram_ctrl_lc_escalation	7.000s	496.330us	1	1	100.00
sec_cm_key_local_esc				0	1	0.00
	sram_ctrl_sec_cm	2.000s	14.294us	0	1	0.00
sec_cm_init_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	2.000s	14.294us	0	1	0.00
sec_cm_scramble_key_sideload				1	1	100.00
	sram_ctrl_smoke	14.000s	953.641us	1	1	100.00
sec_cm_tlul_fifo_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	2.000s	14.294us	0	1	0.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	184.000s	5897.160us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-:], 'b0}) <= ; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
	sram_ctrl_max_throughput	14845172978915737244154344290331503750207922709557961908137577946459794249715	102	UVM_FATAL @ 27256588 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 27256588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	42331705349935895490828016048894320072285396808447009846604359415593599863695	102	UVM_FATAL @ 92994638 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 92994638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	43626346573502972323985186141471369240326434885473861827438196881410129901618	86	UVM_ERROR @ 114984334 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x42) UVM_INFO @ 114984334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_/rtl/tlul_adapter_sram.sv,636): Assertion rvalidHighReqFifoEmpty has failed
	sram_ctrl_mubi_enc_err	75625492924940272981982081135262728597246114187358817868882548920019436963579	89	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,636): (time 49509235 PS) Assertion tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.rvalidHighReqFifoEmpty has failed UVM_ERROR @ 49509235 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 49509235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	80573762667284534683014780706014550201434344028232204928796766577668105887444	90	UVM_ERROR @ 14293648 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 14293648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---