Simulation Results: uart

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.45 %
  • code
  • 77.55 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.66 %
  • line
  • 99.24 %
  • branch
  • 97.42 %
  • toggle
  • 88.53 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.000s 88.788us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 43.888us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 89.066us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 59.252us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 113.453us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 27.413us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 89.066us 1 1 100.00
uart_csr_aliasing 2.000s 113.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 40.000s 23517.647us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.000s 88.788us 1 1 100.00
uart_tx_rx 40.000s 23517.647us 1 1 100.00
parity_error 2 2 100.00
uart_intr 20.000s 22036.759us 1 1 100.00
uart_rx_parity_err 13.000s 35370.172us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 40.000s 23517.647us 1 1 100.00
uart_intr 20.000s 22036.759us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 108.000s 75668.741us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 28.000s 31857.036us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 20.000s 27123.059us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 20.000s 22036.759us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 20.000s 22036.759us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 20.000s 22036.759us 1 1 100.00
perf 1 1 100.00
uart_perf 24.000s 10082.886us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.000s 9800.112us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.000s 9800.112us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.000s 1785.639us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 14.000s 40297.387us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 703.890us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 13.000s 7200.865us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 217.000s 138982.659us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 75.000s 59582.807us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 11.841us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 44.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.000s 69.190us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.000s 69.190us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 43.888us 1 1 100.00
uart_csr_rw 2.000s 89.066us 1 1 100.00
uart_csr_aliasing 2.000s 113.453us 1 1 100.00
uart_same_csr_outstanding 2.000s 286.650us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 43.888us 1 1 100.00
uart_csr_rw 2.000s 89.066us 1 1 100.00
uart_csr_aliasing 2.000s 113.453us 1 1 100.00
uart_same_csr_outstanding 2.000s 286.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 158.360us 1 1 100.00
uart_tl_intg_err 1.000s 383.005us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 383.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 10.000s 1076.425us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr
uart_noise_filter 66359871629565937841980298375472077589769265326019670903228333902418883248118 83
UVM_ERROR @ 367519285 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 367519285 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_ERROR @ 367519285 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 367519285 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 398479285 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 18, clk_pulses: 0