Simulation Results: ac_range_check

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.91 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 57.88 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 30.000s 1399.106us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 45.000s 4790.686us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 39.447us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 175.650us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 24.000s 3384.027us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 16.000s 380.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 18.575us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 175.650us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 380.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 61.843us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 34.000s 9446.385us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 120.000s 17019.652us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 18.450us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 16.994us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 75.505us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 75.505us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 39.447us 1 1 100.00
ac_range_check_csr_rw 3.000s 175.650us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 380.599us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 188.708us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 39.447us 1 1 100.00
ac_range_check_csr_rw 3.000s 175.650us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 380.599us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 188.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 16.000s 12946.791us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 16.000s 12946.791us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 16.000s 12946.791us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 16.000s 12946.791us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 96.000s 19478.090us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 29.328us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 128.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 253.000s 1566.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 26.000s 7076.083us 1 1 100.00