Simulation Results: aes/masked

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.17 %
  • code
  • 95.19 %
  • assert
  • 98.14 %
  • func
  • 68.20 %
  • block
  • 95.85 %
  • line
  • 97.57 %
  • branch
  • 89.64 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 96.750us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 109.722us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 59.774us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 272.807us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 286.342us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 558.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 70.726us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 272.807us 1 1 100.00
aes_csr_aliasing 2.000s 558.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 109.722us 1 1 100.00
aes_config_error 3.000s 225.888us 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 109.722us 1 1 100.00
aes_config_error 3.000s 225.888us 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 95.324us 1 1 100.00
aes_b2b 12.000s 274.901us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 109.722us 1 1 100.00
aes_config_error 3.000s 225.888us 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
aes_alert_reset 6.000s 124.338us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 80.862us 1 1 100.00
aes_config_error 3.000s 225.888us 1 1 100.00
aes_alert_reset 6.000s 124.338us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 134.522us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 837.111us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 291.597us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 124.338us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 95.324us 1 1 100.00
aes_sideload 4.000s 133.121us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 793.023us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 5.000s 286.708us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 266.312us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 69.168us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 108.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 108.755us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.774us 1 1 100.00
aes_csr_rw 2.000s 272.807us 1 1 100.00
aes_csr_aliasing 2.000s 558.848us 1 1 100.00
aes_same_csr_outstanding 2.000s 108.323us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.774us 1 1 100.00
aes_csr_rw 2.000s 272.807us 1 1 100.00
aes_csr_aliasing 2.000s 558.848us 1 1 100.00
aes_same_csr_outstanding 2.000s 108.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 135.545us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 230.209us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 165.445us 1 1 100.00
aes_sec_cm 6.000s 3769.929us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 165.445us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 124.338us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 109.722us 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
aes_alert_reset 6.000s 124.338us 1 1 100.00
aes_core_fi 4.000s 145.931us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 266.312us 1 1 100.00
aes_config_error 3.000s 225.888us 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
aes_core_fi 4.000s 145.931us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 304.473us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 74.544us 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 95.324us 1 1 100.00
aes_sideload 4.000s 133.121us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 74.544us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 74.544us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 74.544us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 74.544us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 74.544us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 95.324us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 16.000s 793.542us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
aes_ctr_fi 2.000s 57.696us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 16.000s 793.542us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 16.000s 793.542us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_ctr_fi 2.000s 57.696us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 16.000s 793.542us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
aes_ctr_fi 2.000s 57.696us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 124.338us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
aes_ctr_fi 2.000s 57.696us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
aes_ctr_fi 2.000s 57.696us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_ctr_fi 2.000s 57.696us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_ghash_fi 2.000s 94.580us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 16.000s 793.542us 1 1 100.00
aes_control_fi 2.000s 64.942us 1 1 100.00
aes_cipher_fi 2.000s 69.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 2191.681us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 317065165037958567226975047843781749159393664227984333510913603559131383657 472
UVM_FATAL @ 2191680992 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 2191680992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---