Simulation Results: alert_handler

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 80.34 %
  • code
  • 86.49 %
  • assert
  • 96.93 %
  • func
  • 57.59 %
  • block
  • 98.14 %
  • line
  • 99.39 %
  • branch
  • 96.40 %
  • toggle
  • 81.76 %
  • FSM
  • 68.42 %
Validation stages
V1
100.00%
V2
84.21%
V2S
87.50%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 130.000s 2748.443us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 13.000s 1810.032us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 17.000s 151.258us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 146.000s 1044.633us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 312.000s 18327.569us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 15.000s 566.955us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 17.000s 151.258us 1 1 100.00
alert_handler_csr_aliasing 312.000s 18327.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 248.000s 1969.452us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 40.000s 2543.406us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 3279.000s 29046.875us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 46.000s 1766.118us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 130.000s 2748.443us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 25.000s 131.097us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 65.000s 2282.762us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 683.000s 29305.699us 1 1 100.00
lpg 1 2 50.00
alert_handler_lpg 0.000s 0.000us 0 1 0.00
alert_handler_lpg_stub_clk 1020.000s 13163.364us 1 1 100.00
stress_all 0 1 0.00
alert_handler_stress_all 2879.000s 26184.966us 0 1 0.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 17.000s 997.579us 1 1 100.00
alert_handler_alert_accum_saturation 0 1 0.00
alert_handler_alert_accum_saturation 4.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
alert_handler_intr_test 4.000s 11.853us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 21.000s 822.309us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 21.000s 822.309us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 13.000s 1810.032us 1 1 100.00
alert_handler_csr_rw 17.000s 151.258us 1 1 100.00
alert_handler_csr_aliasing 312.000s 18327.569us 1 1 100.00
alert_handler_same_csr_outstanding 34.000s 783.483us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 13.000s 1810.032us 1 1 100.00
alert_handler_csr_rw 17.000s 151.258us 1 1 100.00
alert_handler_csr_aliasing 312.000s 18327.569us 1 1 100.00
alert_handler_same_csr_outstanding 34.000s 783.483us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 183.000s 2516.003us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 183.000s 2516.003us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 183.000s 2516.003us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 183.000s 2516.003us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 709.000s 8823.586us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
alert_handler_tl_intg_err 10.000s 97.465us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 10.000s 97.465us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 183.000s 2516.003us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 130.000s 2748.443us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 130.000s 2748.443us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 130.000s 2748.443us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 130.000s 2748.443us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 46.000s 1766.118us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 0.000s 0.000us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 46.000s 1766.118us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3279.000s 29046.875us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3279.000s 29046.875us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 26.000s 794.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 73.000s 7073.312us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes
alert_handler_lpg 10061853434455772254844945940066033809843166305146473138347217819878262537034 None
Job timed out after 60 minutes
UVM_ERROR (alert_handler_scoreboard.sv:491) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state
alert_handler_stress_all 33392142154517235396155148321087975901200999522613818861524870671573315627830 126
UVM_ERROR @ 26184965616 ps: (alert_handler_scoreboard.sv:491) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 5 [0x5]) reg name: alert_handler_reg_block.classd_state
UVM_INFO @ 26184965616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
alert_handler_alert_accum_saturation 103267221263863422140446016747909823304631504794041873522673457621013216047828 88
UVM_ERROR @ 0 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 0 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---