| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 0 | 1 | 0.00 | |||
| clkmgr_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| trans_enables | 0 | 1 | 0.00 | |||
| clkmgr_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clk_status | 0 | 1 | 0.00 | |||
| clkmgr_clk_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jitter | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| clkmgr_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_*/seq_lib/clkmgr_regwen_vseq.sv,*|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes. | ||||
| default | None | 1005 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| cover_reg_top | None | 1005 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| Job killed most likely because its dependent job failed. | ||||
| clkmgr_smoke | 88530645364991796114101620910910697505370136313359184800704847283711795761616 | None | ||
| clkmgr_frequency | 97099934556225898972273952251540882786132901970876006707447596400565759420550 | None | ||
| clkmgr_frequency_timeout | 49381423938927942275810263964316821590308126403517527671760035475377822036256 | None | ||
| clkmgr_peri | 95930003114611370488503902738410549759567939267065067373200268265378699325814 | None | ||
| clkmgr_trans | 106105819840093504034592229851994156719910155652192002904731986941040344925281 | None | ||
| clkmgr_clk_status | 20308713292003006821019646454645952676658186250776930697927958049361418247733 | None | ||
| clkmgr_idle_intersig_mubi | 14794281939439602623171974549488704069084846251742213736958742318463330697231 | None | ||
| clkmgr_regwen | 112977840819460281365355056503805746470937316988857637869548932369007650336013 | None | ||
| clkmgr_sec_cm | 100447496584310444893145395482508157289458487761230395943059642789508832668337 | None | ||
| clkmgr_stress_all_with_rand_reset | 40080912071141331413150838221721565012675477153950752175658237106638468011635 | None | ||
| clkmgr_stress_all | 109140107363296551714244185798841464410408245659431436212018223127443815184719 | None | ||
| clkmgr_alert_test | 37928857170110237722752363563389970587942961125512818111438231348671366071839 | None | ||
| clkmgr_shadow_reg_errors | 380060229177474964354878711871893233348557308820990444784391826706504619218 | None | ||
| clkmgr_shadow_reg_errors_with_csr_rw | 99631758790067979958481489733333361684367690780425055261790014737784162985790 | None | ||
| clkmgr_tl_errors | 53932805829520648677382765608083996928611143698829952429041129908437323495135 | None | ||
| clkmgr_tl_intg_err | 20181059232431764297411163000207422702683377056211528648143844695109384788313 | None | ||
| clkmgr_csr_hw_reset | 67300280699269008883303702233412594205737957156240485843159662954817815450575 | None | ||
| clkmgr_csr_rw | 97659315394323971126830087849418218004679707671873653912433553004027878653791 | None | ||
| clkmgr_csr_bit_bash | 64278768541447162860524259958486204901326508383113583418934017256748887878925 | None | ||
| clkmgr_csr_aliasing | 108524886174434098501190782204381055124865287148640253528824029924120852161766 | None | ||
| clkmgr_same_csr_outstanding | 87698816187542846241217723370723262893313413023838283960975857342501514776421 | None | ||
| clkmgr_csr_mem_rw_with_rand_reset | 80616246327004011128808621238314228864219333020837270380269203780837102467811 | None | ||
| clkmgr | None | None | ||
| clkmgr | None | None | ||