Simulation Results: edn/edn0

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.49 %
  • code
  • 86.97 %
  • assert
  • 95.58 %
  • func
  • 49.93 %
  • block
  • 94.60 %
  • line
  • 96.98 %
  • branch
  • 88.49 %
  • toggle
  • 77.92 %
  • FSM
  • 84.50 %
Validation stages
V1
100.00%
V2
85.71%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 17.807us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 16.343us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 14.105us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 36.545us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 74.203us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 25.114us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 14.105us 1 1 100.00
edn_csr_aliasing 2.000s 74.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 145.132us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 145.132us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 145.132us 1 1 100.00
interrupts 0 1 0.00
edn_intr 2.000s 5.158us 0 1 0.00
alerts 1 1 100.00
edn_alert 2.000s 99.614us 1 1 100.00
errs 0 1 0.00
edn_err 1.000s 11.043us 0 1 0.00
disable 2 2 100.00
edn_disable 1.000s 12.192us 1 1 100.00
edn_disable_auto_req_mode 1.000s 31.321us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.000s 347.779us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 55.142us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 67.412us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 240.453us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 240.453us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 16.343us 1 1 100.00
edn_csr_rw 1.000s 14.105us 1 1 100.00
edn_csr_aliasing 2.000s 74.203us 1 1 100.00
edn_same_csr_outstanding 2.000s 32.908us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 16.343us 1 1 100.00
edn_csr_rw 1.000s 14.105us 1 1 100.00
edn_csr_aliasing 2.000s 74.203us 1 1 100.00
edn_same_csr_outstanding 2.000s 32.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 615.172us 1 1 100.00
edn_tl_intg_err 2.000s 317.208us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 18.626us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 99.614us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 615.172us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 615.172us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 615.172us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 615.172us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 99.614us 1 1 100.00
edn_sec_cm 5.000s 615.172us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 99.614us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 317.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.000s 6094.908us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_main_sm.sv,44): Assertion u_state_regs_A has failed
edn_intr 30169976615568569519139430379707041373555821134889544196396715641949877795888 126
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,44): (time 5157545 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
UVM_ERROR @ 5157545 ps: (edn_main_sm.sv:44) [ASSERT FAILED] u_state_regs_A
UVM_INFO @ 5157545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_ack_sm.sv,54): Assertion u_state_regs_A has failed
edn_err 53873409033990404624884181589089148400353119177870823588291571908978805714851 145
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,54): (time 11043436 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
UVM_ERROR @ 11043436 ps: (edn_ack_sm.sv:54) [ASSERT FAILED] u_state_regs_A
UVM_INFO @ 11043436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---