| V1 |
|
100.00% |
| V2 |
|
88.24% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke_en_cdc_prim | 2.000s | 186.551us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.000s | 112.494us | 1 | 1 | 100.00 | |
| gpio_smoke | 2.000s | 140.115us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.000s | 33.509us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.000s | 128.622us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 1.000s | 66.068us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 8.000s | 698.852us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 3.000s | 495.875us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.000s | 58.463us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 1.000s | 66.068us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 3.000s | 495.875us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 2.000s | 34.739us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 2.000s | 65.512us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.000s | 18.558us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 2.000s | 45.338us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 3.000s | 333.390us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.000s | 312.136us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 8.000s | 823.741us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 3.000s | 434.687us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.000s | 169.397us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 1.000s | 2.564us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 1.000s | 16.853us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 2.000s | 57.767us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 3.000s | 73.747us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 3.000s | 73.747us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| gpio_csr_rw | 1.000s | 66.068us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.000s | 60.306us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 3.000s | 495.875us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.000s | 128.622us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| gpio_csr_rw | 1.000s | 66.068us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.000s | 60.306us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 3.000s | 495.875us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.000s | 128.622us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 2.000s | 82.865us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.000s | 222.763us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 2.000s | 82.865us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 1.000s | 131.739us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 14.000s | 989.354us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 2.000s | 21.730us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | ||||
| gpio_same_csr_outstanding | 108793191859453972064779748548025167638013417572065085939937792718425435574565 | 86 |
UVM_ERROR @ 60306393 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (13888512 [0xd3ec00] vs 13888513 [0xd3ec01]) addr 0xf1321754 read out mismatch
UVM_INFO @ 60306393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| gpio_stress_all | 73501538351615403029324543670398543441113929674061089033675846276542904771335 | 84 |
UVM_ERROR @ 2563836 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3204078872 [0xbefa5d18])
UVM_INFO @ 2563836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) | ||||
| gpio_stress_all_with_rand_reset | 61529518779225541536359274917224445135191951361159333017684306028429598546589 | 327 |
UVM_FATAL @ 989354280 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 989354280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|