Simulation Results: hmac

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.74 %
  • code
  • 96.08 %
  • assert
  • 95.86 %
  • func
  • 29.28 %
  • block
  • 97.64 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.000s 643.723us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 17.313us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 18.277us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.000s 266.781us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 2908.377us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 427.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 18.277us 1 1 100.00
hmac_csr_aliasing 7.000s 2908.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 60.000s 4057.384us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 59.000s 8462.112us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 174.000s 5533.445us 1 1 100.00
hmac_test_sha384_vectors 20.000s 414.447us 1 1 100.00
hmac_test_sha512_vectors 27.000s 932.423us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 972.297us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 310.802us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 277.963us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.000s 472.986us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 169.000s 3915.156us 1 1 100.00
error 1 1 100.00
hmac_error 26.000s 5349.759us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 83.000s 7611.191us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.000s 643.723us 1 1 100.00
hmac_long_msg 60.000s 4057.384us 1 1 100.00
hmac_back_pressure 59.000s 8462.112us 1 1 100.00
hmac_datapath_stress 169.000s 3915.156us 1 1 100.00
hmac_burst_wr 19.000s 472.986us 1 1 100.00
hmac_stress_all 168.000s 17292.324us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.000s 643.723us 1 1 100.00
hmac_long_msg 60.000s 4057.384us 1 1 100.00
hmac_back_pressure 59.000s 8462.112us 1 1 100.00
hmac_datapath_stress 169.000s 3915.156us 1 1 100.00
hmac_wipe_secret 83.000s 7611.191us 1 1 100.00
hmac_test_sha256_vectors 174.000s 5533.445us 1 1 100.00
hmac_test_sha384_vectors 20.000s 414.447us 1 1 100.00
hmac_test_sha512_vectors 27.000s 932.423us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 972.297us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 310.802us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 277.963us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.000s 643.723us 1 1 100.00
hmac_long_msg 60.000s 4057.384us 1 1 100.00
hmac_back_pressure 59.000s 8462.112us 1 1 100.00
hmac_datapath_stress 169.000s 3915.156us 1 1 100.00
hmac_burst_wr 19.000s 472.986us 1 1 100.00
hmac_error 26.000s 5349.759us 1 1 100.00
hmac_wipe_secret 83.000s 7611.191us 1 1 100.00
hmac_test_sha256_vectors 174.000s 5533.445us 1 1 100.00
hmac_test_sha384_vectors 20.000s 414.447us 1 1 100.00
hmac_test_sha512_vectors 27.000s 932.423us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 972.297us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 310.802us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 277.963us 1 1 100.00
hmac_stress_all 168.000s 17292.324us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 168.000s 17292.324us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 12.344us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 41.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 323.492us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 323.492us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 17.313us 1 1 100.00
hmac_csr_rw 2.000s 18.277us 1 1 100.00
hmac_csr_aliasing 7.000s 2908.377us 1 1 100.00
hmac_same_csr_outstanding 3.000s 138.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 17.313us 1 1 100.00
hmac_csr_rw 2.000s 18.277us 1 1 100.00
hmac_csr_aliasing 7.000s 2908.377us 1 1 100.00
hmac_same_csr_outstanding 3.000s 138.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.000s 375.084us 1 1 100.00
hmac_sec_cm 2.000s 532.781us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 375.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.000s 643.723us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.000s 821.593us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 206.000s 10869.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.000s 294.235us 1 1 100.00