| V1 |
|
100.00% |
| V2 |
|
87.80% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_smoke | 1 | 1 | 100.00 | |||
| i2c_host_smoke | 128.000s | 1916.604us | 1 | 1 | 100.00 | |
| target_smoke | 1 | 1 | 100.00 | |||
| i2c_target_smoke | 9.000s | 2096.188us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| i2c_csr_hw_reset | 1.000s | 20.679us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| i2c_csr_rw | 2.000s | 18.842us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| i2c_csr_bit_bash | 4.000s | 1080.921us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| i2c_csr_aliasing | 2.000s | 359.561us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| i2c_csr_mem_rw_with_rand_reset | 1.000s | 132.408us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| i2c_csr_rw | 2.000s | 18.842us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 2.000s | 359.561us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_error_intr | 0 | 1 | 0.00 | |||
| i2c_host_error_intr | 2.000s | 89.994us | 0 | 1 | 0.00 | |
| host_stress_all | 0 | 1 | 0.00 | |||
| i2c_host_stress_all | 2.000s | 198.240us | 0 | 1 | 0.00 | |
| host_maxperf | 1 | 1 | 100.00 | |||
| i2c_host_perf | 1419.000s | 6402.338us | 1 | 1 | 100.00 | |
| host_override | 1 | 1 | 100.00 | |||
| i2c_host_override | 2.000s | 21.109us | 1 | 1 | 100.00 | |
| host_fifo_watermark | 1 | 1 | 100.00 | |||
| i2c_host_fifo_watermark | 1858.000s | 11690.013us | 1 | 1 | 100.00 | |
| host_fifo_overflow | 1 | 1 | 100.00 | |||
| i2c_host_fifo_overflow | 923.000s | 3143.395us | 1 | 1 | 100.00 | |
| host_fifo_reset | 3 | 3 | 100.00 | |||
| i2c_host_fifo_reset_fmt | 2.000s | 287.958us | 1 | 1 | 100.00 | |
| i2c_host_fifo_fmt_empty | 51.000s | 490.131us | 1 | 1 | 100.00 | |
| i2c_host_fifo_reset_rx | 2.000s | 142.101us | 1 | 1 | 100.00 | |
| host_fifo_full | 1 | 1 | 100.00 | |||
| i2c_host_fifo_full | 514.000s | 32718.758us | 1 | 1 | 100.00 | |
| host_timeout | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 12.000s | 2843.457us | 1 | 1 | 100.00 | |
| i2c_host_mode_toggle | 1 | 1 | 100.00 | |||
| i2c_host_mode_toggle | 4.000s | 234.136us | 1 | 1 | 100.00 | |
| target_glitch | 0 | 1 | 0.00 | |||
| i2c_target_glitch | 3.000s | 930.314us | 0 | 1 | 0.00 | |
| target_stress_all | 1 | 1 | 100.00 | |||
| i2c_target_stress_all | 32.000s | 8505.618us | 1 | 1 | 100.00 | |
| target_maxperf | 1 | 1 | 100.00 | |||
| i2c_target_perf | 5.000s | 10731.625us | 1 | 1 | 100.00 | |
| target_fifo_empty | 2 | 2 | 100.00 | |||
| i2c_target_stress_rd | 48.000s | 1488.416us | 1 | 1 | 100.00 | |
| i2c_target_intr_smoke | 7.000s | 757.155us | 1 | 1 | 100.00 | |
| target_fifo_reset | 2 | 2 | 100.00 | |||
| i2c_target_fifo_reset_acq | 2.000s | 104.930us | 1 | 1 | 100.00 | |
| i2c_target_fifo_reset_tx | 2.000s | 217.464us | 1 | 1 | 100.00 | |
| target_fifo_full | 2 | 3 | 66.67 | |||
| i2c_target_stress_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_target_stress_rd | 48.000s | 1488.416us | 1 | 1 | 100.00 | |
| i2c_target_intr_stress_wr | 22.000s | 7944.909us | 1 | 1 | 100.00 | |
| target_timeout | 1 | 1 | 100.00 | |||
| i2c_target_timeout | 8.000s | 2594.502us | 1 | 1 | 100.00 | |
| target_clock_stretch | 0 | 1 | 0.00 | |||
| i2c_target_stretch | 4.000s | 10011.429us | 0 | 1 | 0.00 | |
| bad_address | 1 | 1 | 100.00 | |||
| i2c_target_bad_addr | 4.000s | 976.826us | 1 | 1 | 100.00 | |
| target_mode_glitch | 1 | 1 | 100.00 | |||
| i2c_target_hrst | 2.000s | 91.751us | 1 | 1 | 100.00 | |
| target_fifo_watermark | 2 | 2 | 100.00 | |||
| i2c_target_fifo_watermarks_acq | 3.000s | 186.229us | 1 | 1 | 100.00 | |
| i2c_target_fifo_watermarks_tx | 2.000s | 410.433us | 1 | 1 | 100.00 | |
| host_mode_config_perf | 2 | 2 | 100.00 | |||
| i2c_host_perf | 1419.000s | 6402.338us | 1 | 1 | 100.00 | |
| i2c_host_perf_precise | 3.000s | 75.259us | 1 | 1 | 100.00 | |
| host_mode_clock_stretching | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 12.000s | 2843.457us | 1 | 1 | 100.00 | |
| target_mode_tx_stretch_ctrl | 1 | 1 | 100.00 | |||
| i2c_target_tx_stretch_ctrl | 3.000s | 292.424us | 1 | 1 | 100.00 | |
| target_mode_nack_generation | 3 | 3 | 100.00 | |||
| i2c_target_nack_acqfull | 4.000s | 549.542us | 1 | 1 | 100.00 | |
| i2c_target_nack_acqfull_addr | 3.000s | 1062.684us | 1 | 1 | 100.00 | |
| i2c_target_nack_txstretch | 3.000s | 146.722us | 1 | 1 | 100.00 | |
| host_mode_halt_on_nak | 1 | 1 | 100.00 | |||
| i2c_host_may_nack | 6.000s | 923.853us | 1 | 1 | 100.00 | |
| target_mode_smbus_maxlen | 1 | 1 | 100.00 | |||
| i2c_target_smbus_maxlen | 3.000s | 1191.132us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| i2c_alert_test | 1.000s | 61.585us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| i2c_intr_test | 1.000s | 73.609us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 3.000s | 274.802us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 3.000s | 274.802us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 1.000s | 20.679us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 2.000s | 18.842us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 2.000s | 359.561us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 1.000s | 21.867us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 1.000s | 20.679us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 2.000s | 18.842us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 2.000s | 359.561us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 1.000s | 21.867us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| i2c_sec_cm | 1.000s | 437.010us | 1 | 1 | 100.00 | |
| i2c_tl_intg_err | 2.000s | 82.815us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| i2c_tl_intg_err | 2.000s | 82.815us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_host_stress_all_with_rand_reset | 2.000s | 213.041us | 0 | 1 | 0.00 | |
| target_error_intr | 0 | 1 | 0.00 | |||
| i2c_target_unexp_stop | 2.000s | 149.524us | 0 | 1 | 0.00 | |
| target_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_target_stress_all_with_rand_reset | 6.000s | 380.450us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between | ||||
| i2c_host_error_intr | 84332444427844037298564479744586631761573805183602496537706700826461979821700 | 140 |
UVM_ERROR @ 89993674 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 89993674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_host_stress_all | 43063804312466967753076905661209619941018876466142057482767308556416282325734 | 106 |
UVM_ERROR @ 198239512 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 198239512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between | ||||
| i2c_target_glitch | 85179070145858432971481598511847728266090979456531855756137098463452575083339 | 93 |
UVM_ERROR @ 930314226 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 930314226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| i2c_target_stress_wr | 78914485668469966163391144474069105611884785070398435563520252980919445393497 | None |
Job timed out after 60 minutes
|
|
| UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! | ||||
| i2c_target_stretch | 67047880437475273644938838453137629936346286961534915196489314119156065353826 | 87 |
UVM_FATAL @ 10011428589 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011428589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) | ||||
| i2c_target_unexp_stop | 84365994257379226377290930850035326017629325037455892233092821330003862852173 | 87 |
UVM_ERROR @ 149523546 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 84 [0x54])
UVM_INFO @ 149523546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| i2c_host_stress_all_with_rand_reset | 94265889487347554978818041532716750668498724041364510208640883830429899894507 | 93 |
UVM_ERROR @ 213041181 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 213041181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_target_stress_all_with_rand_reset | 92053416724706027338566454997541264688553956859576288402957013999527262067798 | 93 |
UVM_ERROR @ 380449698 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 380449698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|