Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.69 %
  • code
  • 92.78 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 96.66 %
  • line
  • 97.29 %
  • branch
  • 91.49 %
  • toggle
  • 87.12 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 28.527us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 54.458us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 17.272us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 64.273us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 151.282us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 38.090us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 17.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 151.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 92.241us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1322.492us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 19.703us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 155.036us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 842.036us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_prog_failure 2.000s 155.036us 1 1 100.00
lc_ctrl_errors 5.000s 842.036us 1 1 100.00
lc_ctrl_security_escalation 4.000s 240.147us 1 1 100.00
lc_ctrl_jtag_state_failure 13.000s 2297.588us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 109.095us 1 1 100.00
lc_ctrl_jtag_errors 21.000s 3868.680us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 300.140us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 728.197us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 109.095us 1 1 100.00
lc_ctrl_jtag_errors 21.000s 3868.680us 1 1 100.00
lc_ctrl_jtag_access 5.000s 4855.968us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 3689.550us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 196.062us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 149.001us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 4478.473us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 4047.284us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 183.476us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 386.741us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 117.173us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 564.918us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 15.533us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.000s 1772.249us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 70.303us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 66.101us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 66.101us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 54.458us 1 1 100.00
lc_ctrl_csr_rw 2.000s 17.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 151.282us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 79.211us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 54.458us 1 1 100.00
lc_ctrl_csr_rw 2.000s 17.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 151.282us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 79.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 242.863us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 242.863us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1322.492us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 1293.291us 1 1 100.00
lc_ctrl_sec_cm 3.000s 272.830us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 240.147us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 92.241us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 728.197us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 982.117us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 982.117us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 391.612us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 290.469us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 290.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 21.000s 11026.567us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 46046896537514922445249322662186651785102737549865216521076920279739030034294 6868
UVM_ERROR @ 11026567081 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11026567081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---