Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.81 %
  • code
  • 93.93 %
  • assert
  • 95.97 %
  • func
  • 88.54 %
  • block
  • 97.02 %
  • line
  • 97.60 %
  • branch
  • 92.45 %
  • toggle
  • 88.06 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 19.601us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.370us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 132.257us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 27.187us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.265us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 145.610us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 132.257us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 54.985us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 634.933us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.744us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 37.619us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 330.136us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_prog_failure 2.000s 37.619us 1 1 100.00
lc_ctrl_errors 6.000s 330.136us 1 1 100.00
lc_ctrl_security_escalation 4.000s 1867.256us 1 1 100.00
lc_ctrl_jtag_state_failure 31.000s 1933.954us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 702.905us 1 1 100.00
lc_ctrl_jtag_errors 34.000s 4150.440us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 238.560us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1786.429us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 702.905us 1 1 100.00
lc_ctrl_jtag_errors 34.000s 4150.440us 1 1 100.00
lc_ctrl_jtag_access 4.000s 1340.815us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 2476.358us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 49.733us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 112.313us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 8787.719us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 401.014us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 84.687us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 516.864us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 53.592us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 324.582us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 18.454us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 57.000s 6367.515us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 20.915us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 374.318us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 374.318us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.370us 1 1 100.00
lc_ctrl_csr_rw 2.000s 132.257us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.265us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 22.398us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.370us 1 1 100.00
lc_ctrl_csr_rw 2.000s 132.257us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.265us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 22.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 168.085us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 168.085us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 634.933us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 359.804us 1 1 100.00
lc_ctrl_sec_cm 4.000s 2132.662us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 1867.256us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 54.985us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1786.429us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1283.603us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1283.603us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 828.855us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 233.068us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 233.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 28.000s 3756.599us 1 1 100.00