Simulation Results: mbx

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.53 %
  • code
  • 90.25 %
  • assert
  • 97.05 %
  • func
  • 75.29 %
  • block
  • 96.12 %
  • line
  • 95.61 %
  • branch
  • 89.73 %
  • toggle
  • 85.41 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 65.000s 11347.187us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 19.745us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 16.052us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 5.000s 1290.187us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 50.630us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 6.024us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 16.052us 1 1 100.00
mbx_csr_aliasing 2.000s 50.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 5.000s 290.812us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 81.000s 39520.097us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 10.000s 4336.250us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 19.000s 670.745us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 15.029us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 40.769us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 2.354us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 2.354us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 19.745us 1 1 100.00
mbx_csr_rw 1.000s 16.052us 1 1 100.00
mbx_csr_aliasing 2.000s 50.630us 1 1 100.00
mbx_same_csr_outstanding 1.000s 98.526us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 19.745us 1 1 100.00
mbx_csr_rw 1.000s 16.052us 1 1 100.00
mbx_csr_aliasing 2.000s 50.630us 1 1 100.00
mbx_same_csr_outstanding 1.000s 98.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 1.000s 31.513us 1 1 100.00
mbx_tl_intg_err 2.000s 174.726us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress 51583105633184589862496585984940985383100786228592778086464185748662459147718 279
UVM_ERROR @ 290811803 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (746987899 [0x2c86217b] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 290811803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 113944498466283528335166648471480886284135371938359971228924445887014134409731 85
UVM_ERROR @ 2353599 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15699) { a_addr: 'h2ba07450 a_data: 'h8a4e60cc a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'he7 a_opcode: 'h1 a_user: 'h2649b d_param: 'h0 d_source: 'he7 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2353599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 102679681685829859297334215950432154103853027265986353147341282494548046974351 86
UVM_ERROR @ 6024248 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@17604) { a_addr: 'hf074e070 a_data: 'hf20b2a8e a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'ha2 a_opcode: 'h1 a_user: 'h27ce6 d_param: 'h0 d_source: 'ha2 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6024248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---