Simulation Results: otbn

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.27 %
  • code
  • 95.33 %
  • assert
  • 89.60 %
  • func
  • 97.88 %
  • block
  • 99.40 %
  • line
  • 99.58 %
  • branch
  • 92.61 %
  • toggle
  • 91.69 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 219.998us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 14.908us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 14.633us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 36.019us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 57.358us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 43.344us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 14.633us 1 1 100.00
otbn_csr_aliasing 4.000s 57.358us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 55.000s 2699.607us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 46.000s 2051.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 15.000s 105.811us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 58.000s 220.555us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 53.000s 185.574us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 66.000s 209.475us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 5.000s 58.196us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 8.834us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 41.364us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 19.525us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 14.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 155.587us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 155.587us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 14.908us 1 1 100.00
otbn_csr_rw 4.000s 14.633us 1 1 100.00
otbn_csr_aliasing 4.000s 57.358us 1 1 100.00
otbn_same_csr_outstanding 8.000s 25.347us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 14.908us 1 1 100.00
otbn_csr_rw 4.000s 14.633us 1 1 100.00
otbn_csr_aliasing 4.000s 57.358us 1 1 100.00
otbn_same_csr_outstanding 8.000s 25.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 45.288us 1 1 100.00
otbn_dmem_err 8.000s 17.735us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 7.000s 104.724us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 22.190us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 18.508us 1 1 100.00
otbn_urnd_err 4.000s 28.195us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 29.012us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 15.828us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 43.998us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 16.000s 267.428us 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 46.000s 230.241us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 219.998us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 17.735us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 45.288us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 267.428us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 58.196us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 45.288us 1 1 100.00
otbn_dmem_err 8.000s 17.735us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 8.834us 0 1 0.00
otbn_illegal_mem_acc 4.000s 29.012us 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 45.288us 1 1 100.00
otbn_dmem_err 8.000s 17.735us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 8.834us 0 1 0.00
otbn_illegal_mem_acc 4.000s 29.012us 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 58.196us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 45.288us 1 1 100.00
otbn_dmem_err 8.000s 17.735us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 8.834us 0 1 0.00
otbn_illegal_mem_acc 4.000s 29.012us 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 13.292us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 143.769us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 44.000s 516.233us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 44.000s 516.233us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 11.000s 198.717us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 69.474us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 160.546us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 160.546us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 62.450us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 53.000s 185.574us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 13.000s 203.882us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 24.146us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 188.000s 1264.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 64.000s 1782.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 71.158us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_zero_state_err_urnd 1726730636141514980254639737886047673199457786934501542582105052673970820101 112
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8834006 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 8834006 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8834006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---