Simulation Results

Simulation Results: rv_dm/use_dmi_interface

09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.43 %

code
74.24 %

assert
96.04 %

func
92.02 %

block
89.47 %

line
89.17 %

branch
71.41 %

toggle
75.68 %

FSM
60.71 %

Validation stages

V1		96.30%
V2		69.57%
V2S		71.43%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	33.000s	2349.039us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	37.000s	301.015us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	526.924us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	53.000s	17364.971us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	38.000s	730.522us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	47.000s	8831.880us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	35.000s	1846.206us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	117.000s	78164.615us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	93.000s	52605.034us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	325.597us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	31.000s	364.419us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	137.786us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	29.000s	91.113us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	590.658us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	33.000s	852.063us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	29.000s	89.094us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	33.000s	1137.980us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	325.597us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	303.256us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	388.834us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	137.786us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	49.019us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	33.000s	1548.749us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	88.218us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	48.000s	5144.900us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	47.000s	2303.882us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	33.000s	256.649us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	47.000s	2303.882us	1	1	100.00
	rv_dm_csr_rw	31.000s	88.218us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	77.240us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	81.092us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	33.000s	2349.039us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	570.641us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	32.000s	109.255us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	31.000s	346.369us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	41.000s	2473.334us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	321.000s	300000.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	571.000s	300000.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	308.000s	300000.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	178.000s	300000.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	31.000s	631.609us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	38.000s	3222.219us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	33.000s	175.393us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	31.000s	135.769us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm_rand_reset	43.000s	2887.807us	1	1	100.00
	rv_dm_tap_fsm	37.000s	5898.696us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	432.155us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	35.000s	49.904us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	31.000s	68.353us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	36.000s	1361.137us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	36.000s	1361.137us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	47.000s	2303.882us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	1548.749us	1	1	100.00
	rv_dm_csr_rw	31.000s	88.218us	1	1	100.00
	rv_dm_same_csr_outstanding	31.000s	577.237us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	47.000s	2303.882us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	1548.749us	1	1	100.00
	rv_dm_csr_rw	31.000s	88.218us	1	1	100.00
	rv_dm_same_csr_outstanding	31.000s	577.237us	1	1	100.00

V2S

5/7 passed

71.43 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_tl_intg_err	36.000s	827.209us	1	1	100.00
	rv_dm_sec_cm	31.000s	243.425us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	827.209us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	38.000s	3222.219us	1	1	100.00
	rv_dm_debug_disabled	30.000s	21.951us	0	1	0.00
sec_cm_lc_dft_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	38.000s	3222.219us	1	1	100.00
	rv_dm_debug_disabled	30.000s	21.951us	0	1	0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	33.000s	2349.039us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				0	1	0.00
	rv_dm_buffered_enable	30.000s	105.853us	0	1	0.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	56.408us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	56.408us	1	1	100.00
sec_cm_exec_ctrl_mubi				0	1	0.00
	rv_dm_buffered_enable	30.000s	105.853us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	33.000s	253.570us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	204.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	54465613382050120266116794138445081778153275171614119035506754300893768591358	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	92667923880063596719262005394394767676079057249689650510426833850918008355160	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	13068868549743916469899804138200585794132390518384825373104309760849694926147	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	51208022718404836581202294301726808697410416993970393199344063381733655061360	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	79885141358243504874582084534233149967314301225481131319660180896634993005667	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	51264264297775454177812939945224995140249990909697611123638974487743887727520	87	UVM_ERROR @ 91112852 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 91112852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	50274538313260600902638837350564603809067947533837137689745798920665126715198	98	UVM_ERROR @ 253570374 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 253570374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	5411101744252904354064884484758876210498985856987560323242241926963232648702	87	UVM_ERROR @ 135769373 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 135769373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	39792571395774139962018191312496356676193648392457130357687449467542533525066	88	UVM_ERROR @ 49903577 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 49903577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	16108425434251779828381547588887833871702137639895100773665410304631633625153	87	UVM_ERROR @ 631609096 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1354260446 [0x50b85fde] vs 0 [0x0]) UVM_INFO @ 631609096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed
	rv_dm_debug_disabled	26818534922865120712567799041335252509900189486494404590358481968958205654206	91	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv,42): (time 21950803 PS) Assertion tb.dut.enable_checker.DebugRequestNeedsDebug_A has failed UVM_ERROR @ 21950803 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) UVM_INFO @ 21950803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])
	rv_dm_buffered_enable	77122832423686635618229425036881903866705875109033075193923747478764376937050	92	UVM_ERROR @ 105852654 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) UVM_INFO @ 105852654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---