Simulation Results: rv_timer

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 304.210us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 14.689us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 22.527us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 116.058us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.585us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 20.545us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 22.527us 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 7.000s 23093.591us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1098.874us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 86.000s 211835.057us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 86.000s 211835.057us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 4053.931us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 26.211us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 54.308us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.000s 220.601us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.000s 220.601us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 14.689us 1 1 100.00
rv_timer_csr_rw 1.000s 22.527us 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.585us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 43.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 14.689us 1 1 100.00
rv_timer_csr_rw 1.000s 22.527us 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.585us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 43.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 42.052us 1 1 100.00
rv_timer_tl_intg_err 1.000s 400.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 400.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 28.048us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.000s 170.290us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 44.000s 6576.391us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 103093753350618110517820794516696320282272092332249602284933940099261707898820 84
UVM_ERROR @ 170290333 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 170290333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 69427056445996353701279150774044269287313100685920999127735287262334014064855 86
UVM_FATAL @ 23093591259 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x531bed04) == 0x1
UVM_INFO @ 23093591259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---