Simulation Results

Simulation Results: spi_device/1r1w

09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
82.13 %

code
91.62 %

assert
87.53 %

func
67.25 %

block
98.30 %

line
98.75 %

branch
96.91 %

toggle
81.25 %

FSM
89.58 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	96.000s	13002.586us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	2.000s	60.014us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	4.000s	37.161us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	22.000s	365.372us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	8.000s	314.700us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	5.000s	236.652us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	4.000s	37.161us	1	1	100.00
	spi_device_csr_aliasing	8.000s	314.700us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	1.000s	25.280us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	3.000s	218.330us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	1.000s	34.249us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	2.000s	1.307us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	2.000s	3.181us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	3.000s	41.862us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	3.000s	41.862us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	6.000s	1979.615us	1	1	100.00
	spi_device_tpm_sts_read	2.000s	18.013us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	14.000s	2122.376us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	33.000s	9069.476us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	17.000s	38883.047us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	17.000s	38883.047us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	11.000s	1504.067us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	11.000s	1504.067us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	11.000s	1504.067us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	11.000s	1504.067us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	11.000s	1504.067us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	5.000s	438.051us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	65.000s	24786.480us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	65.000s	24786.480us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	65.000s	24786.480us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	6.000s	219.801us	1	1	100.00
	spi_device_read_buffer_direct	6.000s	505.660us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	65.000s	24786.480us	1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	155.000s	31936.378us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	5.000s	431.874us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	5.000s	431.874us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	96.000s	13002.586us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	92.000s	17655.778us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	3.000s	186.197us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	1.000s	15.314us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	2.000s	26.982us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.000s	76.657us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.000s	76.657us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	60.014us	1	1	100.00
	spi_device_csr_rw	4.000s	37.161us	1	1	100.00
	spi_device_csr_aliasing	8.000s	314.700us	1	1	100.00
	spi_device_same_csr_outstanding	3.000s	46.960us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	60.014us	1	1	100.00
	spi_device_csr_rw	4.000s	37.161us	1	1	100.00
	spi_device_csr_aliasing	8.000s	314.700us	1	1	100.00
	spi_device_same_csr_outstanding	3.000s	46.960us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_sec_cm	2.000s	779.195us	1	1	100.00
	spi_device_tl_intg_err	15.000s	2160.331us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	15.000s	2160.331us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	2.000s	135.305us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	spi_device_mem_parity	28262130862914836816990656390849637241201451916660166874242901029915247692763	87	UVM_ERROR @ 1127326 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[57] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_ERROR @ 1127326 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) ERROR: VHPI NOTFOUND Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[953] not found within the scope . UVM_ERROR @ 1127326 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[953] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	68770656209031576420403281728554029684567085074308459806277861006509377674317	85	UVM_ERROR @ 1047605 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc872b [110011001000011100101011] vs 0x0 [0]) UVM_ERROR @ 1086605 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa126d6 [101000010010011011010110] vs 0x0 [0]) UVM_ERROR @ 1168605 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17903 [10111100100000011] vs 0x0 [0]) UVM_ERROR @ 1261605 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x56a37d [10101101010001101111101] vs 0x0 [0]) UVM_ERROR @ 1278605 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ec185 [1111101100000110000101] vs 0x0 [0])