Simulation Results: sram_ctrl/main

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.82 %
  • code
  • 83.39 %
  • assert
  • 95.91 %
  • func
  • 93.16 %
  • block
  • 94.59 %
  • line
  • 95.56 %
  • branch
  • 90.13 %
  • toggle
  • 81.20 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 16.000s 9434.573us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 21.228us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.685us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 256.851us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.492us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 369.318us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 33.685us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.492us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 128.000s 43089.047us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 53.000s 5777.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 50.000s 1709.242us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 181.000s 20638.676us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1064.000s 101122.343us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 271.000s 25728.805us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 9643.757us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 272.000s 5767.961us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 18.000s 1566.368us 1 1 100.00
sram_ctrl_partial_access_b2b 199.000s 27967.478us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 4.000s 1314.213us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 715.115us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2763.882us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 587.000s 66034.771us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1408.724us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2920.000s 74679.383us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 48.993us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 81.601us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 81.601us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.228us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.685us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.492us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 32.676us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.228us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.685us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.492us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 32.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3915.765us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 1.000s 2.339us 0 1 0.00
sram_ctrl_tl_intg_err 2.000s 218.636us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 1.000s 2.339us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 218.636us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 587.000s 66034.771us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 587.000s 66034.771us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.685us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 272.000s 5767.961us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 272.000s 5767.961us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 272.000s 5767.961us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 9643.757us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 669.642us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3915.765us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 2760.059us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 16.000s 9434.573us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 16.000s 9434.573us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 272.000s 5767.961us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 1.000s 2.339us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 9643.757us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 1.000s 2.339us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 2.339us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 16.000s 9434.573us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 2.339us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 2091.421us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 108553670128828921441161250949774947742056948324623354982305517553509852154164 102
UVM_FATAL @ 1314212989 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1314212989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46602939552338599348453992789677610573360701126762442032160025176904508064835 102
UVM_FATAL @ 2763882386 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 2763882386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 42850161824041870488143685518055338477948880047587751065770143048217882981883 90
UVM_ERROR @ 2338906 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2338906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---