Simulation Results: sram_ctrl/ret

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.98 %
  • code
  • 83.67 %
  • assert
  • 95.88 %
  • func
  • 90.40 %
  • block
  • 94.77 %
  • line
  • 95.80 %
  • branch
  • 90.61 %
  • toggle
  • 81.62 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 457.651us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.066us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 27.370us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 233.258us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.638us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 29.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 27.370us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.638us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 452.291us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 361.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 703.000s 18006.125us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 257.000s 11404.554us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 44.000s 12048.957us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 259.000s 11291.791us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 347.184us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 559.000s 13500.985us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 17.000s 793.592us 1 1 100.00
sram_ctrl_partial_access_b2b 129.000s 5816.379us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 2.000s 23.971us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 40.809us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 32.015us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 353.000s 11155.133us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 26.881us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2750.000s 25254.884us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 64.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 23.588us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 23.588us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.066us 1 1 100.00
sram_ctrl_csr_rw 2.000s 27.370us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.638us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.338us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.066us 1 1 100.00
sram_ctrl_csr_rw 2.000s 27.370us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.638us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 455.498us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 3.000s 175.994us 1 1 100.00
sram_ctrl_sec_cm 2.000s 4.060us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 2.000s 4.060us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 175.994us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 353.000s 11155.133us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 353.000s 11155.133us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 27.370us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 559.000s 13500.985us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 559.000s 13500.985us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 559.000s 13500.985us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 347.184us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 47.150us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 455.498us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 42.216us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 457.651us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 457.651us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 559.000s 13500.985us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 2.000s 4.060us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 347.184us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 2.000s 4.060us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 2.000s 4.060us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 457.651us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 2.000s 4.060us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 267.314us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 105373954515687619512622506080759098989462867391600618557111180165075338639155 102
UVM_FATAL @ 23970728 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 23970728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 74381273927909178240117614740079917025925232365566077943527844488860264268602 102
UVM_FATAL @ 32014574 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 32014574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 41385203078402656208416215801003851320769877193866020359890929532557555522689 90
UVM_ERROR @ 4060292 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4060292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---