Simulation Results: aes/masked

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.96 %
  • code
  • 95.41 %
  • assert
  • 98.29 %
  • func
  • 70.18 %
  • block
  • 96.05 %
  • line
  • 97.89 %
  • branch
  • 90.24 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 92.791us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 112.283us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 71.970us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 79.371us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 462.572us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 103.958us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 82.916us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 79.371us 1 1 100.00
aes_csr_aliasing 2.000s 103.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 112.283us 1 1 100.00
aes_config_error 4.000s 104.207us 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 112.283us 1 1 100.00
aes_config_error 4.000s 104.207us 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 312.307us 1 1 100.00
aes_b2b 8.000s 141.252us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 112.283us 1 1 100.00
aes_config_error 4.000s 104.207us 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
aes_alert_reset 5.000s 464.800us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 105.308us 1 1 100.00
aes_config_error 4.000s 104.207us 1 1 100.00
aes_alert_reset 5.000s 464.800us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 66.554us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1227.728us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 11.000s 5887.831us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 464.800us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 312.307us 1 1 100.00
aes_sideload 4.000s 404.385us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 75.127us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 77.000s 1440.611us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 122.671us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 89.882us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 67.473us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 67.473us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 71.970us 1 1 100.00
aes_csr_rw 2.000s 79.371us 1 1 100.00
aes_csr_aliasing 2.000s 103.958us 1 1 100.00
aes_same_csr_outstanding 1.000s 117.298us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 71.970us 1 1 100.00
aes_csr_rw 2.000s 79.371us 1 1 100.00
aes_csr_aliasing 2.000s 103.958us 1 1 100.00
aes_same_csr_outstanding 1.000s 117.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 357.710us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 208.791us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 700.202us 1 1 100.00
aes_tl_intg_err 3.000s 504.511us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 504.511us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 464.800us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 112.283us 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
aes_alert_reset 5.000s 464.800us 1 1 100.00
aes_core_fi 3.000s 120.460us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 122.671us 1 1 100.00
aes_config_error 4.000s 104.207us 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
aes_core_fi 3.000s 120.460us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 122.831us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 85.415us 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 312.307us 1 1 100.00
aes_sideload 4.000s 404.385us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 85.415us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 85.415us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 85.415us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 85.415us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 85.415us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 312.307us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 297.125us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
aes_ctr_fi 2.000s 98.007us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 297.125us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 297.125us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_ctr_fi 2.000s 98.007us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 297.125us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
aes_ctr_fi 2.000s 98.007us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 464.800us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
aes_ctr_fi 2.000s 98.007us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
aes_ctr_fi 2.000s 98.007us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_ctr_fi 2.000s 98.007us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_ghash_fi 3.000s 131.764us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 4.000s 297.125us 1 1 100.00
aes_control_fi 2.000s 52.942us 1 1 100.00
aes_cipher_fi 3.000s 155.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 104.084us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 30003053465491474563491292474640724390191023426908192822340872879739911287247 162
UVM_INFO @ 104083743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---