Simulation Results: aes/unmasked

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.30 %
  • code
  • 91.49 %
  • assert
  • 97.75 %
  • func
  • 66.67 %
  • block
  • 91.79 %
  • line
  • 94.26 %
  • branch
  • 85.05 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 82.597us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 91.732us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 112.094us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 147.740us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 638.678us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 684.946us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 249.523us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 147.740us 1 1 100.00
aes_csr_aliasing 4.000s 684.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 91.732us 1 1 100.00
aes_config_error 3.000s 420.747us 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 91.732us 1 1 100.00
aes_config_error 3.000s 420.747us 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 89.714us 1 1 100.00
aes_b2b 3.000s 77.942us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 91.732us 1 1 100.00
aes_config_error 3.000s 420.747us 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
aes_alert_reset 3.000s 107.970us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 74.575us 1 1 100.00
aes_config_error 3.000s 420.747us 1 1 100.00
aes_alert_reset 3.000s 107.970us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 78.726us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 341.433us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 278.835us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 107.970us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 89.714us 1 1 100.00
aes_sideload 3.000s 174.098us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 151.178us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 19.000s 3404.810us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 68.127us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 52.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 92.413us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 92.413us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 112.094us 1 1 100.00
aes_csr_rw 2.000s 147.740us 1 1 100.00
aes_csr_aliasing 4.000s 684.946us 1 1 100.00
aes_same_csr_outstanding 1.000s 107.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 112.094us 1 1 100.00
aes_csr_rw 2.000s 147.740us 1 1 100.00
aes_csr_aliasing 4.000s 684.946us 1 1 100.00
aes_same_csr_outstanding 1.000s 107.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 120.357us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 232.685us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 867.225us 1 1 100.00
aes_tl_intg_err 2.000s 227.778us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 227.778us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 107.970us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 91.732us 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
aes_alert_reset 3.000s 107.970us 1 1 100.00
aes_core_fi 2.000s 105.446us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 68.127us 1 1 100.00
aes_config_error 3.000s 420.747us 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
aes_core_fi 2.000s 105.446us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 139.288us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 63.578us 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 89.714us 1 1 100.00
aes_sideload 3.000s 174.098us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.578us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.578us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 63.578us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 63.578us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 63.578us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 89.714us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 331.881us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
aes_ctr_fi 2.000s 50.005us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 331.881us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 331.881us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_ctr_fi 2.000s 50.005us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 331.881us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
aes_ctr_fi 2.000s 50.005us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 107.970us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
aes_ctr_fi 2.000s 50.005us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
aes_ctr_fi 2.000s 50.005us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_ctr_fi 2.000s 50.005us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_ghash_fi 2.000s 63.037us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 331.881us 1 1 100.00
aes_control_fi 2.000s 80.316us 1 1 100.00
aes_cipher_fi 3.000s 117.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 9.000s 367.798us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 14127919924227791125733082067931722122534967868010860289274022817057462143647 233
UVM_INFO @ 367797922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---