Simulation Results: clkmgr

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.63 %
  • code
  • 68.81 %
  • assert
  • 89.26 %
  • func
  • 68.83 %
  • line
  • 82.11 %
  • branch
  • 87.42 %
  • cond
  • 76.96 %
  • toggle
  • 97.55 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.790s 16.718us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.340s 104.220us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 10.620s 1330.663us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.750s 5.508us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.840s 19.616us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
clkmgr_csr_aliasing 0.750s 5.508us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 19.847us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.170s 27.013us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.930s 37.821us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.790s 16.718us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.720s 10.915us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.590s 4.928us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.720s 10.915us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.150s 53.420us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.900s 34.891us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.420s 144.469us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.420s 144.469us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.340s 104.220us 1 1 100.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
clkmgr_csr_aliasing 0.750s 5.508us 0 1 0.00
clkmgr_same_csr_outstanding 0.580s 1.445us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.340s 104.220us 1 1 100.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
clkmgr_csr_aliasing 0.750s 5.508us 0 1 0.00
clkmgr_same_csr_outstanding 0.580s 1.445us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.280s 451.897us 1 1 100.00
clkmgr_tl_intg_err 0.740s 13.310us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 35.819us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 35.819us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 35.819us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 35.819us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.850s 19.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.740s 13.310us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.720s 10.915us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.590s 4.928us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 35.819us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.060s 52.295us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.280s 451.897us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.710s 16.670us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.280s 451.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.670s 13.918us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.030s 25.732us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 901511695670962248365379365617031623175341701272354657230036079166770740431 76
UVM_INFO @ 10915493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 89328566656659590288226534578256179054450756338532402461512255191806007273303 78
UVM_INFO @ 4928396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 40904856132594736809146373786620995990324042247120037500784543705176969223079 79
UVM_INFO @ 25732138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 113287534824623550390548135931337180783760927000902353598843744923540297153847 77
UVM_INFO @ 53419864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 18807626638168692718654015109580112060510450642901015653736085522083478385998 74
UVM_INFO @ 13918360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 90355963895470255662939535184184806264214918376647074626599400017601367828819 75
UVM_INFO @ 18999848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 65880028187410139323146238756950462767325006133250187869347309556778248032835 85
UVM_INFO @ 13310095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 63126925965650533916639710685788950727189159482873418167491391176160199999916 75
UVM_INFO @ 16669732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 66778959223061146256699403995945034287902270408204188151835214693207621883512 75
UVM_INFO @ 5508110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 78336191351679945716545375596317812117785159840946560712916350764017536392453 75
UVM_INFO @ 1330662894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 91190731287885771460134654131005091064595429226669873794627066946518362841846 75
UVM_INFO @ 1445478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---