Simulation Results: dma

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.63 %
  • code
  • 92.20 %
  • assert
  • 95.55 %
  • func
  • 63.13 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 622.696us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 343.236us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1158.411us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 55.645us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 24.408us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 6426.622us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 2277.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 20.976us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 24.408us 1 1 100.00
dma_csr_aliasing 6.000s 2277.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 38.000s 11963.621us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 494.000s 187847.951us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 274.000s 24846.599us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 274.000s 24846.599us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 494.000s 187847.951us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 145.000s 12199.242us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 274.000s 24846.599us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 7.000s 469.919us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 118.000s 9062.994us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 16.841us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 53.828us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 226.177us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 226.177us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 55.645us 1 1 100.00
dma_csr_rw 1.000s 24.408us 1 1 100.00
dma_csr_aliasing 6.000s 2277.705us 1 1 100.00
dma_same_csr_outstanding 2.000s 378.992us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 55.645us 1 1 100.00
dma_csr_rw 1.000s 24.408us 1 1 100.00
dma_csr_aliasing 6.000s 2277.705us 1 1 100.00
dma_same_csr_outstanding 2.000s 378.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 16.000s 93.912us 1 1 100.00
dma_generic_stress 145.000s 12199.242us 1 1 100.00
dma_handshake_stress 274.000s 24846.599us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 326.524us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 369.347us 1 1 100.00
dma_sec_cm 2.000s 21.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 71.000s 28690.723us 1 1 100.00
dma_longer_transfer 4.000s 275.505us 1 1 100.00
dma_stress_all_with_rand_reset 19.000s 717.175us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 70244375002469538494844579895587584001864134970037743857639028820178078314118 119
UVM_INFO @ 717174573ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---