Simulation Results: edn/edn0

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.60 %
  • code
  • 79.81 %
  • assert
  • 95.01 %
  • func
  • 78.97 %
  • line
  • 97.01 %
  • branch
  • 89.82 %
  • cond
  • 84.50 %
  • toggle
  • 79.35 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.770s 124.402us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.780s 75.986us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.880s 24.872us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.680s 1083.224us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.400s 88.079us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.110s 43.640us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.880s 24.872us 1 1 100.00
edn_csr_aliasing 1.400s 88.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.280s 46.677us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.280s 46.677us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.280s 46.677us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 23.177us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 24.342us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 26.335us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 22.390us 1 1 100.00
edn_disable_auto_req_mode 1.260s 172.995us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.060s 410.049us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 16.037us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.070s 86.578us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.840s 217.210us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.840s 217.210us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.780s 75.986us 1 1 100.00
edn_csr_rw 0.880s 24.872us 1 1 100.00
edn_csr_aliasing 1.400s 88.079us 1 1 100.00
edn_same_csr_outstanding 0.970s 176.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.780s 75.986us 1 1 100.00
edn_csr_rw 0.880s 24.872us 1 1 100.00
edn_csr_aliasing 1.400s 88.079us 1 1 100.00
edn_same_csr_outstanding 0.970s 176.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.850s 2411.026us 1 1 100.00
edn_tl_intg_err 1.240s 348.895us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 33.631us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 24.342us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.850s 2411.026us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.850s 2411.026us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.850s 2411.026us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.850s 2411.026us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 24.342us 1 1 100.00
edn_sec_cm 5.850s 2411.026us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 24.342us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.240s 348.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 8.510s 373.910us 1 1 100.00