Simulation Results: edn/edn1

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.25 %
  • code
  • 85.20 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 98.33 %
  • branch
  • 93.72 %
  • cond
  • 89.54 %
  • toggle
  • 95.57 %
  • FSM
  • 48.86 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.030s 20.108us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 17.190us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 38.243us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.560s 139.753us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.020s 105.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.470s 140.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 38.243us 1 1 100.00
edn_csr_aliasing 1.020s 105.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.960s 33.438us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.960s 33.438us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.960s 33.438us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.730s 70.034us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 30.670us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 46.600us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 20.646us 1 1 100.00
edn_disable_auto_req_mode 1.050s 52.916us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.130s 469.637us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 64.712us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.760s 25.136us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.050s 271.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.050s 271.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 17.190us 1 1 100.00
edn_csr_rw 0.720s 38.243us 1 1 100.00
edn_csr_aliasing 1.020s 105.793us 1 1 100.00
edn_same_csr_outstanding 0.860s 62.065us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 17.190us 1 1 100.00
edn_csr_rw 0.720s 38.243us 1 1 100.00
edn_csr_aliasing 1.020s 105.793us 1 1 100.00
edn_same_csr_outstanding 0.860s 62.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.700s 523.848us 1 1 100.00
edn_tl_intg_err 1.260s 54.062us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 44.158us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 30.670us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.700s 523.848us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.700s 523.848us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.700s 523.848us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.700s 523.848us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 30.670us 1 1 100.00
edn_sec_cm 3.700s 523.848us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 30.670us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.260s 54.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 21.200s 3868.506us 1 1 100.00