Simulation Results: hmac

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.37 %
  • code
  • 97.44 %
  • assert
  • 97.36 %
  • func
  • 43.32 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.63 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.940s 1401.683us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.720s 22.934us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 29.907us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.850s 417.511us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.330s 1384.088us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.130s 165.003us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 29.907us 1 1 100.00
hmac_csr_aliasing 6.330s 1384.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.170s 2757.462us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 79.440s 3201.955us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.570s 188.290us 1 1 100.00
hmac_test_sha384_vectors 374.140s 42898.760us 1 1 100.00
hmac_test_sha512_vectors 497.420s 30639.656us 1 1 100.00
hmac_test_hmac256_vectors 9.160s 1128.636us 1 1 100.00
hmac_test_hmac384_vectors 7.180s 242.321us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 286.073us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.410s 1093.504us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 685.350s 5199.668us 1 1 100.00
error 1 1 100.00
hmac_error 28.990s 18644.285us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 34.570s 9778.614us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.940s 1401.683us 1 1 100.00
hmac_long_msg 26.170s 2757.462us 1 1 100.00
hmac_back_pressure 79.440s 3201.955us 1 1 100.00
hmac_datapath_stress 685.350s 5199.668us 1 1 100.00
hmac_burst_wr 8.410s 1093.504us 1 1 100.00
hmac_stress_all 111.690s 35585.108us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.940s 1401.683us 1 1 100.00
hmac_long_msg 26.170s 2757.462us 1 1 100.00
hmac_back_pressure 79.440s 3201.955us 1 1 100.00
hmac_datapath_stress 685.350s 5199.668us 1 1 100.00
hmac_wipe_secret 34.570s 9778.614us 1 1 100.00
hmac_test_sha256_vectors 8.570s 188.290us 1 1 100.00
hmac_test_sha384_vectors 374.140s 42898.760us 1 1 100.00
hmac_test_sha512_vectors 497.420s 30639.656us 1 1 100.00
hmac_test_hmac256_vectors 9.160s 1128.636us 1 1 100.00
hmac_test_hmac384_vectors 7.180s 242.321us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 286.073us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.940s 1401.683us 1 1 100.00
hmac_long_msg 26.170s 2757.462us 1 1 100.00
hmac_back_pressure 79.440s 3201.955us 1 1 100.00
hmac_datapath_stress 685.350s 5199.668us 1 1 100.00
hmac_burst_wr 8.410s 1093.504us 1 1 100.00
hmac_error 28.990s 18644.285us 1 1 100.00
hmac_wipe_secret 34.570s 9778.614us 1 1 100.00
hmac_test_sha256_vectors 8.570s 188.290us 1 1 100.00
hmac_test_sha384_vectors 374.140s 42898.760us 1 1 100.00
hmac_test_sha512_vectors 497.420s 30639.656us 1 1 100.00
hmac_test_hmac256_vectors 9.160s 1128.636us 1 1 100.00
hmac_test_hmac384_vectors 7.180s 242.321us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 286.073us 1 1 100.00
hmac_stress_all 111.690s 35585.108us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 111.690s 35585.108us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.570s 40.605us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.710s 22.729us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.870s 53.173us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.870s 53.173us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.720s 22.934us 1 1 100.00
hmac_csr_rw 0.790s 29.907us 1 1 100.00
hmac_csr_aliasing 6.330s 1384.088us 1 1 100.00
hmac_same_csr_outstanding 1.520s 313.309us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.720s 22.934us 1 1 100.00
hmac_csr_rw 0.790s 29.907us 1 1 100.00
hmac_csr_aliasing 6.330s 1384.088us 1 1 100.00
hmac_same_csr_outstanding 1.520s 313.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.950s 90.370us 1 1 100.00
hmac_tl_intg_err 2.590s 781.570us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.590s 781.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.940s 1401.683us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.860s 307.457us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 48.780s 14324.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.320s 245.791us 1 1 100.00