Simulation Results

Simulation Results: i2c

13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.67 %

code
81.53 %

assert
96.19 %

func
79.28 %

line
96.38 %

branch
92.33 %

cond
85.23 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	19.190s	7335.399us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.620s	633.070us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.790s	85.449us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.840s	66.510us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.830s	379.701us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.720s	345.146us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.170s	109.954us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.840s	66.510us	1	1	100.00
	i2c_csr_aliasing	1.720s	345.146us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.790s	48.209us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	47.470s	7550.055us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	54.260s	4862.388us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.680s	86.178us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	40.270s	2902.496us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	28.460s	5722.444us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.390s	143.042us	1	1	100.00
	i2c_host_fifo_fmt_empty	11.980s	1297.970us	1	1	100.00
	i2c_host_fifo_reset_rx	8.250s	595.445us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	124.990s	11568.328us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.760s	966.069us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.830s	78.430us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.220s	2470.106us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	172.980s	81444.747us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.750s	668.701us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	30.770s	1966.273us	1	1	100.00
	i2c_target_intr_smoke	5.290s	1103.850us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.080s	437.818us	1	1	100.00
	i2c_target_fifo_reset_tx	0.840s	251.454us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	42.550s	23167.274us	1	1	100.00
	i2c_target_stress_rd	30.770s	1966.273us	1	1	100.00
	i2c_target_intr_stress_wr	4.990s	21018.376us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.320s	2107.468us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	10.310s	1360.805us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.830s	749.180us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.790s	3537.035us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.480s	695.861us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.140s	2721.836us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	54.260s	4862.388us	1	1	100.00
	i2c_host_perf_precise	12.980s	2683.096us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.760s	966.069us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.920s	142.075us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.390s	498.572us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.530s	542.600us	1	1	100.00
	i2c_target_nack_txstretch	1.620s	136.436us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.300s	251.128us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.910s	545.462us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.800s	17.544us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.860s	96.311us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.970s	1088.100us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.970s	1088.100us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.790s	85.449us	1	1	100.00
	i2c_csr_rw	0.840s	66.510us	1	1	100.00
	i2c_csr_aliasing	1.720s	345.146us	1	1	100.00
	i2c_same_csr_outstanding	1.130s	35.446us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.790s	85.449us	1	1	100.00
	i2c_csr_rw	0.840s	66.510us	1	1	100.00
	i2c_csr_aliasing	1.720s	345.146us	1	1	100.00
	i2c_same_csr_outstanding	1.130s	35.446us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.090s	310.109us	1	1	100.00
	i2c_sec_cm	1.210s	188.812us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.090s	310.109us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	27.140s	694.571us	1
target_error_intr				1
	i2c_target_unexp_stop	1.310s	154.552us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	13.800s	11198.977us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	11882775372047078234260382755448347749149342790696247533910257327481239771191	86	UVM_INFO @ 48208663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	95058577123498550903083513346757395862831607467560839289859833924176343828739	142	UVM_INFO @ 7550055418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	7673586567810942029464159258437158094056894859974682670417876771248773007462	84	UVM_INFO @ 2470105503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	61189094995258744203648344189894305316870926098322908214148044690086807624367	78	UVM_INFO @ 154551689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	104862802713800901731820941196714275119665803898060469986723312833953939815250	99	UVM_INFO @ 694571257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	13229526971192643380392276362046117365600501448726616554957535123231092418800	88	UVM_INFO @ 11198977097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	99789162922732998260715096443142349637627930074332584216160822511139290884379	79	UVM_INFO @ 78429785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---