Simulation Results: kmac/masked

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.56 %
  • code
  • 90.41 %
  • assert
  • 97.84 %
  • func
  • 95.42 %
  • line
  • 98.85 %
  • branch
  • 96.37 %
  • cond
  • 93.60 %
  • toggle
  • 99.84 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 9.950s 653.341us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.930s 24.790us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.080s 36.299us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.090s 1117.780us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.280s 75.419us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.380s 43.721us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.080s 36.299us 1 1 100.00
kmac_csr_aliasing 3.280s 75.419us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.800s 37.700us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.190s 41.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2531.900s 103072.177us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 213.210s 6456.432us 1 1 100.00
test_vectors 7 8 87.50
kmac_test_vectors_sha3_224 34.070s 8464.118us 1 1 100.00
kmac_test_vectors_sha3_256 32.790s 29811.005us 1 1 100.00
kmac_test_vectors_sha3_384 23.830s 1958.079us 1 1 100.00
kmac_test_vectors_sha3_512 0.810s 39.744us 0 1 0.00
kmac_test_vectors_shake_128 192.190s 45738.862us 1 1 100.00
kmac_test_vectors_shake_256 270.170s 87533.908us 1 1 100.00
kmac_test_vectors_kmac 2.620s 102.170us 1 1 100.00
kmac_test_vectors_kmac_xof 2.370s 182.829us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 233.450s 7786.050us 1 1 100.00
app 1 1 100.00
kmac_app 121.400s 6708.141us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 283.090s 56743.108us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 123.660s 7167.997us 1 1 100.00
error 1 1 100.00
kmac_error 348.400s 55135.617us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.860s 3756.447us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.550s 107.566us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 22.070s 3562.359us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.180s 31.517us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 2.230s 767.021us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.220s 66.339us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 850.340s 62601.372us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.900s 39.207us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.980s 70.926us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.920s 141.753us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.920s 141.753us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.930s 24.790us 1 1 100.00
kmac_csr_rw 1.080s 36.299us 1 1 100.00
kmac_csr_aliasing 3.280s 75.419us 1 1 100.00
kmac_same_csr_outstanding 1.840s 125.839us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.930s 24.790us 1 1 100.00
kmac_csr_rw 1.080s 36.299us 1 1 100.00
kmac_csr_aliasing 3.280s 75.419us 1 1 100.00
kmac_same_csr_outstanding 1.840s 125.839us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.590s 95.393us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.590s 95.393us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.590s 95.393us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.590s 95.393us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.550s 265.412us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 28.110s 14593.683us 1 1 100.00
kmac_tl_intg_err 3.770s 238.841us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.770s 238.841us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.220s 66.339us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 9.950s 653.341us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 233.450s 7786.050us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.590s 95.393us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 28.110s 14593.683us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 28.110s 14593.683us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 28.110s 14593.683us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 9.950s 653.341us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.220s 66.339us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 28.110s 14593.683us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 221.810s 32206.635us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 9.950s 653.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 90.830s 20319.731us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_test_vectors_sha3_512 97227925779996774491316890066500674819454350920989527949070900269720204725655 83
UVM_INFO @ 39743511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---