Simulation Results: kmac/unmasked

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.85 %
  • code
  • 88.46 %
  • assert
  • 97.75 %
  • func
  • 92.35 %
  • line
  • 97.20 %
  • branch
  • 94.71 %
  • cond
  • 93.35 %
  • toggle
  • 100.00 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 35.380s 3343.174us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.060s 16.814us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.960s 109.467us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 14.250s 1283.365us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.970s 1925.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.600s 136.256us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.960s 109.467us 1 1 100.00
kmac_csr_aliasing 6.970s 1925.926us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.720s 15.429us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.140s 265.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1005.340s 171716.205us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 432.660s 26349.219us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 26.640s 2542.865us 1 1 100.00
kmac_test_vectors_sha3_256 33.580s 8407.965us 1 1 100.00
kmac_test_vectors_sha3_384 787.950s 12765.884us 1 1 100.00
kmac_test_vectors_sha3_512 13.410s 3600.593us 1 1 100.00
kmac_test_vectors_shake_128 151.830s 38094.302us 1 1 100.00
kmac_test_vectors_shake_256 1499.520s 354041.415us 1 1 100.00
kmac_test_vectors_kmac 1.460s 99.923us 1 1 100.00
kmac_test_vectors_kmac_xof 1.840s 33.631us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 32.930s 1010.743us 1 1 100.00
app 1 1 100.00
kmac_app 115.880s 77966.957us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 150.610s 7137.830us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 52.270s 13363.617us 1 1 100.00
error 1 1 100.00
kmac_error 41.610s 2295.760us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.480s 3321.820us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 26.920s 10210.131us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 19.890s 354.643us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 26.180s 2032.427us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 37.660s 47880.743us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.760s 556.196us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 119.420s 4151.121us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.950s 81.290us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.810s 46.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.690s 95.827us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.690s 95.827us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.060s 16.814us 1 1 100.00
kmac_csr_rw 0.960s 109.467us 1 1 100.00
kmac_csr_aliasing 6.970s 1925.926us 1 1 100.00
kmac_same_csr_outstanding 1.280s 87.583us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.060s 16.814us 1 1 100.00
kmac_csr_rw 0.960s 109.467us 1 1 100.00
kmac_csr_aliasing 6.970s 1925.926us 1 1 100.00
kmac_same_csr_outstanding 1.280s 87.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.340s 382.911us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.340s 382.911us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.340s 382.911us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.340s 382.911us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.860s 174.904us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 54.190s 92425.914us 1 1 100.00
kmac_tl_intg_err 2.400s 155.471us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.400s 155.471us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.760s 556.196us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 35.380s 3343.174us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 32.930s 1010.743us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.340s 382.911us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 54.190s 92425.914us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 54.190s 92425.914us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 54.190s 92425.914us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 35.380s 3343.174us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.760s 556.196us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 54.190s 92425.914us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 178.230s 41787.198us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 35.380s 3343.174us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 84.150s 21715.845us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 64376358503218107329288674219951955063940564581179302482672591394000093752011 93
UVM_INFO @ 10210130914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---