Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.86 %
  • code
  • 85.70 %
  • assert
  • 95.99 %
  • func
  • 93.88 %
  • line
  • 97.69 %
  • branch
  • 96.13 %
  • cond
  • 80.00 %
  • toggle
  • 89.22 %
  • FSM
  • 65.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.830s 318.656us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.790s 49.341us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.990s 19.953us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.470s 64.300us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 82.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.080s 72.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.990s 19.953us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 82.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.410s 997.659us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.170s 366.492us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 20.691us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.260s 110.487us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.060s 957.401us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_prog_failure 2.260s 110.487us 1 1 100.00
lc_ctrl_errors 6.060s 957.401us 1 1 100.00
lc_ctrl_security_escalation 4.750s 1612.295us 1 1 100.00
lc_ctrl_jtag_state_failure 17.770s 1573.033us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.620s 597.764us 1 1 100.00
lc_ctrl_jtag_errors 31.950s 7560.389us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.310s 856.763us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.180s 1160.035us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.620s 597.764us 1 1 100.00
lc_ctrl_jtag_errors 31.950s 7560.389us 1 1 100.00
lc_ctrl_jtag_access 6.110s 1255.675us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.170s 5148.407us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.530s 264.625us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.240s 424.578us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 25.000s 1948.790us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.460s 991.506us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.910s 104.308us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.190s 861.423us 1 1 100.00
lc_ctrl_jtag_alert_test 1.460s 49.689us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.920s 216.070us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 210.648us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 78.430s 21724.320us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.150s 70.861us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 672.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 672.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 49.341us 1 1 100.00
lc_ctrl_csr_rw 0.990s 19.953us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 82.137us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.140s 19.922us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 49.341us 1 1 100.00
lc_ctrl_csr_rw 0.990s 19.953us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 82.137us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.140s 19.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
lc_ctrl_tl_intg_err 2.820s 111.052us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.820s 111.052us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.170s 366.492us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.250s 616.099us 1 1 100.00
lc_ctrl_sec_cm 6.280s 910.090us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.750s 1612.295us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.410s 997.659us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.180s 1160.035us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.860s 1291.633us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.860s 1291.633us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.750s 500.663us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.800s 639.276us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.800s 639.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 64.190s 2682.115us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 72000967055289652021686901719346208676959302040236418282454600640594915985678 5733
UVM_INFO @ 2682114507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---