Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.68 %
  • code
  • 86.41 %
  • assert
  • 95.99 %
  • func
  • 92.63 %
  • line
  • 97.87 %
  • branch
  • 96.43 %
  • cond
  • 79.79 %
  • toggle
  • 88.89 %
  • FSM
  • 69.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.330s 75.212us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.900s 37.927us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 58.340us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.200s 49.502us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 20.399us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.950s 46.329us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 58.340us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 20.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.880s 860.454us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.780s 241.604us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.780s 18.380us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.170s 17.746us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.920s 6293.398us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_prog_failure 1.170s 17.746us 1 1 100.00
lc_ctrl_errors 6.920s 6293.398us 1 1 100.00
lc_ctrl_security_escalation 5.900s 423.959us 1 1 100.00
lc_ctrl_jtag_state_failure 27.420s 2386.325us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.910s 735.426us 1 1 100.00
lc_ctrl_jtag_errors 18.860s 1824.025us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.540s 2614.786us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.270s 2821.674us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.910s 735.426us 1 1 100.00
lc_ctrl_jtag_errors 18.860s 1824.025us 1 1 100.00
lc_ctrl_jtag_access 2.000s 1377.703us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.910s 962.312us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.020s 188.870us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.900s 71.287us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 16.320s 1053.678us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.710s 2246.964us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.390s 69.430us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.610s 97.296us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 185.040us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.490s 110.818us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.060s 33.579us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 47.700s 20535.893us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.940s 18.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.030s 157.052us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.030s 157.052us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.900s 37.927us 1 1 100.00
lc_ctrl_csr_rw 1.030s 58.340us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 20.399us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.400s 144.439us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.900s 37.927us 1 1 100.00
lc_ctrl_csr_rw 1.030s 58.340us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 20.399us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.400s 144.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
lc_ctrl_tl_intg_err 1.300s 241.124us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.300s 241.124us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.780s 241.604us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.870s 966.847us 1 1 100.00
lc_ctrl_sec_cm 6.280s 572.598us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.900s 423.959us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.880s 860.454us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.270s 2821.674us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.790s 2178.678us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.790s 2178.678us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.440s 613.251us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.450s 1502.103us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.450s 1502.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 89.630s 18850.644us 1 1 100.00