Simulation Results: mbx

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.46 %
  • code
  • 90.37 %
  • assert
  • 96.96 %
  • func
  • 84.05 %
  • block
  • 95.80 %
  • line
  • 96.23 %
  • branch
  • 88.83 %
  • toggle
  • 86.04 %
Validation stages
V1
100.00%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 84.000s 20495.812us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 28.924us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 20.959us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 167.050us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 49.122us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 28.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 20.959us 1 1 100.00
mbx_csr_aliasing 1.000s 49.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 7.000s 545.019us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 19.000s 945.535us 1 1 100.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 2.000s 278.014us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 19.000s 8996.604us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 15.232us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 47.374us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 3.276us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 3.276us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 28.924us 1 1 100.00
mbx_csr_rw 2.000s 20.959us 1 1 100.00
mbx_csr_aliasing 1.000s 49.122us 1 1 100.00
mbx_same_csr_outstanding 1.000s 216.527us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 28.924us 1 1 100.00
mbx_csr_rw 2.000s 20.959us 1 1 100.00
mbx_csr_aliasing 1.000s 49.122us 1 1 100.00
mbx_same_csr_outstanding 1.000s 216.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 642.892us 1 1 100.00
mbx_sec_cm 1.000s 12.420us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress 100331035148708506694196108962808293657303649232336962416444134151999543161950 424
UVM_INFO @ 545018605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_imbx_oob 58254831631495561383790926744882662715920150167548503385837373402755886148242 91
UVM_INFO @ 278014005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 45913687871882534780236989308537137699864484516943932847014927344180364566451 85
TL item was: req: (cip_tl_seq_item@16184) { a_addr: 'haab63f50 a_data: 'h84ddd462 a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'ha4 a_opcode: 'h1 a_user: 'h2765c d_param: 'h0 d_source: 'ha4 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3275610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---