Simulation Results: otp_ctrl

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.97 %
  • code
  • 72.10 %
  • assert
  • 92.42 %
  • func
  • 54.39 %
  • line
  • 87.60 %
  • branch
  • 84.14 %
  • cond
  • 86.04 %
  • toggle
  • 66.65 %
  • FSM
  • 36.09 %
Validation stages
V1
100.00%
V2
55.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.870s 200.208us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.110s 1134.560us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.950s 57.400us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.190s 200.140us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.980s 180.871us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.090s 324.065us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.950s 57.400us 1 1 100.00
otp_ctrl_csr_aliasing 3.980s 180.871us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.610s 99.586us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.490s 44.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 116.620s 38450.253us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.930s 884.159us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 8.720s 470.382us 1 1 100.00
otp_ctrl_check_fail 17.540s 900.695us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 2.950s 89.511us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 3.890s 1032.175us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 17.750s 2171.453us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 35.980s 2648.279us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 54.500s 30252.179us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 2.330s 239.493us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 22.320s 2620.215us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.480s 100.215us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.960s 891.079us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.130s 143.645us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.130s 143.645us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.110s 1134.560us 1 1 100.00
otp_ctrl_csr_rw 1.950s 57.400us 1 1 100.00
otp_ctrl_csr_aliasing 3.980s 180.871us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.170s 168.821us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.110s 1134.560us 1 1 100.00
otp_ctrl_csr_rw 1.950s 57.400us 1 1 100.00
otp_ctrl_csr_aliasing 3.980s 180.871us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.170s 168.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
otp_ctrl_tl_intg_err 23.230s 5663.852us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 23.230s 5663.852us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_ctrl_macro_errs 54.500s 30252.179us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_ctrl_macro_errs 54.500s 30252.179us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.800s 306.181us 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.930s 884.159us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 17.540s 900.695us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 2.850s 131.746us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.670s 16804.524us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 2.950s 89.511us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 17.380s 8300.288us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 54.500s 30252.179us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 82.490s 59058.398us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.450s 66.243us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_partition_walk 22720685348177746768304602182718591543491662215958589426892611999945908447764 165291
UVM_INFO @ 38450252553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26884318031809541139502307935578495426462618776919517444220267982261666249090 1723
UVM_INFO @ 884158776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 88200737026952040719776551076861120807407589987909764097714676617384323866500 2316
UVM_INFO @ 89510557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 65051417898988183319810378504029097417303238186271084661019859583674404014573 89
UVM_INFO @ 59058398227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_dai_lock 16408234333007201715547619205326461731225925831185160551997078445506725159167 1904
UVM_INFO @ 131746237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 27528548546030095079376152402996465701744434660803682215014942803192992894447 3138
UVM_INFO @ 1032175397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 6127117638399278598218529817510825748443065279318468261425092062925980705410 650
UVM_INFO @ 239493383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 8207868372419230925197865138615236133167704598552411119199128884553996449006 26503
UVM_INFO @ 2620215308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 81093865160614399110874592929552925512970494432642417618104461060276878223890 16018
UVM_INFO @ 900694532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 15639672627678844979318281231188180874206082824483585350585768513765560971828 25916
UVM_INFO @ 30252179199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 61178325274049491847655823816208127657624585859735056994042879685317011186299 100
UVM_INFO @ 66243282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---