Simulation Results: rom_ctrl/64kb

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.17 %
  • code
  • 97.81 %
  • assert
  • 96.80 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.47 %
  • toggle
  • 99.90 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.710s 4170.821us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.700s 211.741us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.510s 2770.992us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.100s 385.522us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.260s 304.323us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.080s 549.692us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.510s 2770.992us 1 1 100.00
rom_ctrl_csr_aliasing 7.260s 304.323us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.510s 1156.186us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.600s 377.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.810s 301.061us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 17.800s 8745.613us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.800s 2200.240us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.520s 1114.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 11.820s 3688.371us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 11.820s 3688.371us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.700s 211.741us 1 1 100.00
rom_ctrl_csr_rw 6.510s 2770.992us 1 1 100.00
rom_ctrl_csr_aliasing 7.260s 304.323us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.100s 790.059us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.700s 211.741us 1 1 100.00
rom_ctrl_csr_rw 6.510s 2770.992us 1 1 100.00
rom_ctrl_csr_aliasing 7.260s 304.323us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.100s 790.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.390s 1104.857us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 231.230s 1107.458us 1 1 100.00
rom_ctrl_tl_intg_err 100.360s 1584.667us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 231.230s 1107.458us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 231.230s 1107.458us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 231.230s 1107.458us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 231.230s 1107.458us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.710s 4170.821us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.710s 4170.821us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.710s 4170.821us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 100.360s 1584.667us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
rom_ctrl_kmac_err_chk 13.800s 2200.240us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.190s 13095.788us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.390s 1104.857us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 231.230s 1107.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 39.660s 2916.428us 1 1 100.00