Simulation Results: rstmgr

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.04 %
  • code
  • 99.28 %
  • assert
  • 97.25 %
  • func
  • 97.59 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 58.996us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.420s 92.357us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.800s 37.421us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.000s 52.101us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.230s 37.398us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.930s 65.434us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.800s 37.421us 1 1 100.00
rstmgr_csr_aliasing 1.230s 37.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.640s 173.043us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.110s 41.704us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.030s 85.038us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.710s 459.146us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.710s 459.146us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.710s 459.146us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.710s 459.146us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 38.570s 6459.562us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.790s 37.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.090s 49.786us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.090s 49.786us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.420s 92.357us 1 1 100.00
rstmgr_csr_rw 0.800s 37.421us 1 1 100.00
rstmgr_csr_aliasing 1.230s 37.398us 1 1 100.00
rstmgr_same_csr_outstanding 1.160s 39.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.420s 92.357us 1 1 100.00
rstmgr_csr_rw 0.800s 37.421us 1 1 100.00
rstmgr_csr_aliasing 1.230s 37.398us 1 1 100.00
rstmgr_same_csr_outstanding 1.160s 39.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 31.540s 6836.349us 1 1 100.00
rstmgr_tl_intg_err 2.610s 327.058us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 31.540s 6836.349us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 31.540s 6836.349us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.610s 327.058us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.060s 67.037us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.720s 438.524us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.500s 291.605us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 31.540s 6836.349us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 37.421us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 37.421us 1 1 100.00