Simulation Results

Simulation Results: rv_dm/use_dmi_interface

13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
77.69 %

code
73.94 %

assert
96.09 %

func
63.03 %

line
90.22 %

branch
75.21 %

cond
76.46 %

toggle
71.57 %

FSM
56.25 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	1.040s	621.069us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.220s	631.156us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.290s	590.548us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	19.900s	19155.137us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.040s	298.100us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	5.320s	8221.679us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	2.900s	2791.741us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	39.400s	32677.492us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	123.500s	241255.390us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.450s	977.473us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	2.290s	908.690us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.180s	267.609us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.730s	82.728us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	1.590s	504.437us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	2.410s	863.884us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	1.210s	393.232us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.390s	1268.262us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.450s	977.473us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.890s	98.877us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	0.940s	158.461us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.180s	267.609us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.810s	60.793us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.540s	362.353us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.890s	120.032us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	23.450s	2593.770us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	52.310s	5356.994us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	2.070s	69.680us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	52.310s	5356.994us	1	1	100.00
	rv_dm_csr_rw	1.890s	120.032us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.990s	123.090us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.700s	65.568us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	1.040s	621.069us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.190s	336.671us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.720s	143.975us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.830s	353.566us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	2.160s	696.824us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	130.790s	300000.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	70.100s	300000.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	88.380s	300000.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	141.770s	300000.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	1.500s	682.083us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	3.230s	2791.727us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.030s	285.181us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.820s	53.506us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	11.080s	8895.445us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	39.660s	8584.322us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.870s	144.746us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	1.410s	773.606us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.910s	117.162us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	4.010s	205.436us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	4.010s	205.436us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	52.310s	5356.994us	1	1	100.00
	rv_dm_csr_hw_reset	1.540s	362.353us	1	1	100.00
	rv_dm_csr_rw	1.890s	120.032us	1	1	100.00
	rv_dm_same_csr_outstanding	3.130s	186.946us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	52.310s	5356.994us	1	1	100.00
	rv_dm_csr_hw_reset	1.540s	362.353us	1	1	100.00
	rv_dm_csr_rw	1.890s	120.032us	1	1	100.00
	rv_dm_same_csr_outstanding	3.130s	186.946us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	1.100s	502.819us	1	1	100.00
	rv_dm_tl_intg_err	15.580s	5696.024us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	15.580s	5696.024us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	3.230s	2791.727us	1	1	100.00
	rv_dm_debug_disabled	0.980s	59.737us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	3.230s	2791.727us	1	1	100.00
	rv_dm_debug_disabled	0.980s	59.737us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	1.040s	621.069us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	0.980s	297.425us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.860s	297.594us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.860s	297.594us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	0.980s	297.425us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	20.070s	8528.905us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	101.630s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	72101882727536495510713434835777426043886682315860078571769446327140588586026	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	57077315961194002294287727988526849094937202187310770919039720769718408187453	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	69903312805089324547972235062969029355141414120965343265851883095549752938890	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15035275264186716832153150428255007819357189870747664353815893686323572911073	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	75690107654934289740785022469136342118958582079269238622857494952186493822069	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	90405527290829953561070525479995266893168572311240996154782339227333926075542	77	UVM_INFO @ 82727729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	31248381879782129542552208355748011011263804957275168493608286645732199483111	77	UVM_INFO @ 53506400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	21862606137224457596409092759081565512603043873569690525757916744770607694029	122	UVM_INFO @ 8528904679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	7214177137830991948525867625077646307802355637358602385717870807246733216437	77	UVM_INFO @ 682083484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	26594704863498120313844746979316707693591718283063306346301495479668099464547	78	UVM_INFO @ 773605758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---