Simulation Results: rv_timer

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 100.00 %
  • assert
  • 96.50 %
  • func
  • 90.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.840s 91.152us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.660s 15.776us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.780s 15.447us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 342.230us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.740s 58.613us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.910s 38.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.780s 15.447us 1 1 100.00
rv_timer_csr_aliasing 0.740s 58.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.810s 329.105us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.480s 3358.313us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 619.420s 1671376.734us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 619.420s 1671376.734us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 4882.397us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.620s 30.084us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.720s 23.542us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.950s 496.049us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.950s 496.049us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 15.776us 1 1 100.00
rv_timer_csr_rw 0.780s 15.447us 1 1 100.00
rv_timer_csr_aliasing 0.740s 58.613us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 52.323us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 15.776us 1 1 100.00
rv_timer_csr_rw 0.780s 15.447us 1 1 100.00
rv_timer_csr_aliasing 0.740s 58.613us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 52.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.910s 65.247us 1 1 100.00
rv_timer_tl_intg_err 0.940s 193.083us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.940s 193.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.640s 42.931us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.670s 175.521us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 30.530s 3952.864us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 60739998585481672840892928973712484989030038958063514676117954577688204896394 75
UVM_INFO @ 175521346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 95377044801361704185091094869769942461172935492956016571839020669475696561423 75
UVM_INFO @ 329104755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---