Simulation Results: spi_device/1r1w

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.97 %
  • code
  • 93.30 %
  • assert
  • 94.64 %
  • func
  • 72.97 %
  • line
  • 99.07 %
  • branch
  • 98.30 %
  • cond
  • 96.21 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 100.560s 15975.149us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.110s 46.860us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.090s 94.590us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 17.130s 2673.026us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.010s 425.526us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.930s 92.346us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.090s 94.590us 1 1 100.00
spi_device_csr_aliasing 15.010s 425.526us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.940s 18.409us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.970s 70.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.830s 245.582us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.790s 4.444us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.870s 6.450us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.060s 762.693us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.060s 762.693us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.340s 1982.051us 1 1 100.00
spi_device_tpm_sts_read 1.070s 500.815us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.570s 2430.074us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.880s 21662.491us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.010s 17443.380us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.010s 17443.380us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.390s 6247.962us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.390s 6247.962us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.390s 6247.962us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.390s 6247.962us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.390s 6247.962us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 21.250s 10888.013us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 34.150s 20716.159us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 34.150s 20716.159us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 34.150s 20716.159us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.960s 1870.125us 1 1 100.00
spi_device_read_buffer_direct 9.130s 2171.489us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 34.150s 20716.159us 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 350.700s 320966.215us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.290s 1154.586us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.290s 1154.586us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 100.560s 15975.149us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 58.020s 7475.829us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 54.230s 10030.371us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.770s 48.178us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.880s 24.284us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.100s 687.136us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.100s 687.136us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 46.860us 1 1 100.00
spi_device_csr_rw 2.090s 94.590us 1 1 100.00
spi_device_csr_aliasing 15.010s 425.526us 1 1 100.00
spi_device_same_csr_outstanding 1.430s 292.994us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 46.860us 1 1 100.00
spi_device_csr_rw 2.090s 94.590us 1 1 100.00
spi_device_csr_aliasing 15.010s 425.526us 1 1 100.00
spi_device_same_csr_outstanding 1.430s 292.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.120s 303.705us 1 1 100.00
spi_device_tl_intg_err 6.160s 1224.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.160s 1224.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 91.370s 30407.351us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 67564863646857217615860537279368202747850120136910222134617347297510519018525 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3693844 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3693844 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[915])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 67296535273537460464046562420491621925867253495499922686170134736687226594156 76
UVM_ERROR @ 3681029 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa069f3 [101000000110100111110011] vs 0x0 [0])
UVM_ERROR @ 3768029 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x99bdcd [100110011011110111001101] vs 0x0 [0])
UVM_ERROR @ 3852029 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa613fc [101001100001001111111100] vs 0x0 [0])
UVM_ERROR @ 3906029 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcf6b12 [110011110110101100010010] vs 0x0 [0])