Simulation Results: spi_host

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.89 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 89.50 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 9.000s 1666.207us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 44.894us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 44.554us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 87.398us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 22.106us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 37.979us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 44.554us 1 1 100.00
spi_host_csr_aliasing 1.000s 22.106us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 88.686us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 33.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 63.746us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 266.880us 1 1 100.00
spi_host_error_cmd 1.000s 18.729us 1 1 100.00
spi_host_event 14.000s 955.290us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 61.283us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 61.283us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 61.283us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 34.128us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 32.061us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 61.283us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 61.283us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 9.000s 1666.207us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 9.000s 1666.207us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 42.000s 8227.051us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 813.193us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 249.000s 81326.985us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 114.964us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 266.880us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 20.151us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 41.266us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 135.953us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 135.953us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 44.894us 1 1 100.00
spi_host_csr_rw 2.000s 44.554us 1 1 100.00
spi_host_csr_aliasing 1.000s 22.106us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 27.928us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 44.894us 1 1 100.00
spi_host_csr_rw 2.000s 44.554us 1 1 100.00
spi_host_csr_aliasing 1.000s 22.106us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 27.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 81.675us 1 1 100.00
spi_host_sec_cm 1.000s 62.086us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 81.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 83.000s 8414.328us 1 1 100.00