Simulation Results: sram_ctrl/main

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.79 %
  • code
  • 94.45 %
  • assert
  • 96.46 %
  • func
  • 96.47 %
  • line
  • 98.91 %
  • branch
  • 97.90 %
  • cond
  • 95.06 %
  • toggle
  • 89.90 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.640s 958.825us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.640s 18.079us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.840s 14.591us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.390s 150.182us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 44.272us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.940s 356.768us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.840s 14.591us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 44.272us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 274.520s 86217.841us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 107.090s 9761.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 338.630s 35118.749us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 230.350s 4053.966us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 660.870s 41746.319us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 233.020s 23578.897us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 38.180s 9444.953us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 374.600s 17927.176us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.930s 1636.694us 1 1 100.00
sram_ctrl_partial_access_b2b 266.850s 57934.044us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.920s 2693.489us 1 1 100.00
sram_ctrl_throughput_w_partial_write 20.130s 771.311us 1 1 100.00
sram_ctrl_throughput_w_readback 69.950s 1800.469us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 501.490s 115048.776us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.310s 1385.645us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2856.330s 759439.129us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.790s 13.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.720s 87.268us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.720s 87.268us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 18.079us 1 1 100.00
sram_ctrl_csr_rw 0.840s 14.591us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 44.272us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.910s 55.399us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 18.079us 1 1 100.00
sram_ctrl_csr_rw 0.840s 14.591us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 44.272us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.910s 55.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.620s 15307.993us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1627.625us 1 1 100.00
sram_ctrl_tl_intg_err 3.280s 729.052us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1627.625us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.280s 729.052us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 501.490s 115048.776us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 501.490s 115048.776us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.840s 14.591us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 374.600s 17927.176us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 374.600s 17927.176us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 374.600s 17927.176us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 38.180s 9444.953us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.320s 684.760us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.620s 15307.993us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.420s 2754.971us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.640s 958.825us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.640s 958.825us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 374.600s 17927.176us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1627.625us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 38.180s 9444.953us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1627.625us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1627.625us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.640s 958.825us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1627.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.600s 334.935us 1 1 100.00