Simulation Results: sram_ctrl/ret

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.67 %
  • code
  • 92.22 %
  • assert
  • 96.43 %
  • func
  • 95.36 %
  • line
  • 98.35 %
  • branch
  • 96.91 %
  • cond
  • 95.06 %
  • toggle
  • 89.85 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.450s 126.926us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.810s 60.094us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.880s 18.386us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.780s 128.005us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 35.066us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.430s 184.467us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.880s 18.386us 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 35.066us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.840s 71.859us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.330s 1349.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.250s 961.549us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 253.470s 3575.145us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 29.660s 1754.855us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 377.420s 34565.200us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.190s 2868.530us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 292.470s 15800.264us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.670s 302.790us 1 1 100.00
sram_ctrl_partial_access_b2b 248.400s 46467.898us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 53.160s 135.821us 1 1 100.00
sram_ctrl_throughput_w_partial_write 12.160s 501.683us 1 1 100.00
sram_ctrl_throughput_w_readback 40.910s 839.668us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 429.780s 8488.233us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.950s 28.526us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1969.300s 250058.520us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.860s 22.633us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.970s 756.948us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.970s 756.948us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 60.094us 1 1 100.00
sram_ctrl_csr_rw 0.880s 18.386us 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 35.066us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.090s 51.769us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 60.094us 1 1 100.00
sram_ctrl_csr_rw 0.880s 18.386us 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 35.066us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.090s 51.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.700s 263.429us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.210s 907.553us 1 1 100.00
sram_ctrl_tl_intg_err 1.310s 369.595us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.210s 907.553us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.310s 369.595us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 429.780s 8488.233us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 429.780s 8488.233us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.880s 18.386us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 292.470s 15800.264us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 292.470s 15800.264us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 292.470s 15800.264us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.190s 2868.530us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.150s 81.685us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.700s 263.429us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.310s 30.269us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.450s 126.926us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.450s 126.926us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 292.470s 15800.264us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.210s 907.553us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.190s 2868.530us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.210s 907.553us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.210s 907.553us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.450s 126.926us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.210s 907.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.860s 196.321us 1 1 100.00