Simulation Results: uart

 
13/04/2026 16:00:55 DVSim: v1.30.1 sha: 5903df8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.79 %
  • code
  • 96.45 %
  • assert
  • 97.12 %
  • func
  • 48.79 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 96.62 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 6.600s 5763.069us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.720s 16.130us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.650s 14.068us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.260s 255.187us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.740s 31.292us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.760s 23.642us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.650s 14.068us 1 1 100.00
uart_csr_aliasing 0.740s 31.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 23.790s 85997.934us 1 1 100.00
parity 2 2 100.00
uart_smoke 6.600s 5763.069us 1 1 100.00
uart_tx_rx 23.790s 85997.934us 1 1 100.00
parity_error 2 2 100.00
uart_intr 20.200s 16578.360us 1 1 100.00
uart_rx_parity_err 52.810s 51037.400us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 23.790s 85997.934us 1 1 100.00
uart_intr 20.200s 16578.360us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 63.980s 52711.835us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 130.040s 81366.809us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 51.830s 178048.488us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 20.200s 16578.360us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 20.200s 16578.360us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 20.200s 16578.360us 1 1 100.00
perf 1 1 100.00
uart_perf 464.700s 15179.653us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.050s 4202.805us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.050s 4202.805us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 6.720s 5051.318us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 44.510s 38007.497us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.680s 931.810us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 1.270s 2125.494us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 290.260s 85149.614us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 7.420s 27167.816us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.680s 23.021us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.640s 15.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.500s 82.376us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.500s 82.376us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.720s 16.130us 1 1 100.00
uart_csr_rw 0.650s 14.068us 1 1 100.00
uart_csr_aliasing 0.740s 31.292us 1 1 100.00
uart_same_csr_outstanding 0.860s 19.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.720s 16.130us 1 1 100.00
uart_csr_rw 0.650s 14.068us 1 1 100.00
uart_csr_aliasing 0.740s 31.292us 1 1 100.00
uart_same_csr_outstanding 0.860s 19.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.930s 616.515us 1 1 100.00
uart_tl_intg_err 1.220s 188.852us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.220s 188.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.010s 1565.688us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 62504129987724707366041353977501819139097885683408367538850788768136227433298 76
UVM_ERROR @ 4040309673 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 4040320543 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 4040331413 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (22 [0x16] vs 235 [0xeb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4064299763 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 66154074420505917552200893540970891408279817101229214564183088833330781437484 76
UVM_ERROR @ 13510831603 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 13516248313 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 13526706730 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 13529915089 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0