Simulation Results: ac_range_check

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.91 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.95 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
85.71%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 0 1 0.00
ac_range_check_smoke 23.000s 856.487us 0 1 0.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 28.000s 4629.030us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 45.570us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 65.674us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 7455.989us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 3875.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 19.029us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 65.674us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 3875.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 178.516us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 27.000s 10690.690us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 131.000s 5825.017us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 14.800us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 15.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 73.535us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 73.535us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 45.570us 1 1 100.00
ac_range_check_csr_rw 2.000s 65.674us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 3875.984us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 324.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 45.570us 1 1 100.00
ac_range_check_csr_rw 2.000s 65.674us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 3875.984us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 324.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7068.769us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7068.769us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7068.769us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7068.769us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 93.000s 5658.087us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 31.717us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 408.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 239.000s 4620.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 27.000s 5570.046us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke 6170174896735861373475578689534430881307871136369041342796197766033561048717 4250
UVM_INFO @ 856487033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---