Simulation Results: aes/masked

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.83 %
  • code
  • 95.68 %
  • assert
  • 98.29 %
  • func
  • 66.51 %
  • block
  • 95.86 %
  • line
  • 97.51 %
  • branch
  • 89.74 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 64.319us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 166.121us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 91.464us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 60.240us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 610.749us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 495.884us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 263.385us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 60.240us 1 1 100.00
aes_csr_aliasing 3.000s 495.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 166.121us 1 1 100.00
aes_config_error 4.000s 405.713us 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 166.121us 1 1 100.00
aes_config_error 4.000s 405.713us 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 66.211us 1 1 100.00
aes_b2b 21.000s 613.891us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 166.121us 1 1 100.00
aes_config_error 4.000s 405.713us 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
aes_alert_reset 10.000s 10087.593us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 3.000s 58.595us 1 1 100.00
aes_config_error 4.000s 405.713us 1 1 100.00
aes_alert_reset 10.000s 10087.593us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 25.000s 2354.287us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 630.594us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 6.000s 284.829us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 10.000s 10087.593us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 66.211us 1 1 100.00
aes_sideload 27.000s 2923.679us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 405.144us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 225.000s 16181.073us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 870.108us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 66.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 364.773us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 364.773us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 91.464us 1 1 100.00
aes_csr_rw 2.000s 60.240us 1 1 100.00
aes_csr_aliasing 3.000s 495.884us 1 1 100.00
aes_same_csr_outstanding 2.000s 106.922us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 91.464us 1 1 100.00
aes_csr_rw 2.000s 60.240us 1 1 100.00
aes_csr_aliasing 3.000s 495.884us 1 1 100.00
aes_same_csr_outstanding 2.000s 106.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 227.444us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 1752.239us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1005.935us 1 1 100.00
aes_tl_intg_err 3.000s 193.023us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 193.023us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 10.000s 10087.593us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 166.121us 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
aes_alert_reset 10.000s 10087.593us 0 1 0.00
aes_core_fi 3.000s 81.461us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 870.108us 1 1 100.00
aes_config_error 4.000s 405.713us 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
aes_core_fi 3.000s 81.461us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.932us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 63.758us 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 66.211us 1 1 100.00
aes_sideload 27.000s 2923.679us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.758us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.758us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 63.758us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 63.758us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 63.758us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 66.211us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 30.000s 10034.155us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
aes_ctr_fi 2.000s 65.320us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 30.000s 10034.155us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 30.000s 10034.155us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_ctr_fi 2.000s 65.320us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 30.000s 10034.155us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
aes_ctr_fi 2.000s 65.320us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 10.000s 10087.593us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
aes_ctr_fi 2.000s 65.320us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
aes_ctr_fi 2.000s 65.320us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_ctr_fi 2.000s 65.320us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 30.000s 10034.155us 0 1 0.00
aes_ghash_fi 3.000s 78.746us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 30.000s 10034.155us 0 1 0.00
aes_control_fi 2.000s 50.650us 1 1 100.00
aes_cipher_fi 3.000s 60.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 5773.020us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 8854460610701785559296222312696407671836206737777435159807980336360579895506 2292
UVM_INFO @ 10087592726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 92769667869039203030972634376378308682966347385902617529980477755281473012851 821113
UVM_INFO @ 16181072815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 20767750029700468012599624598576084037262435061764562253605193367083725932941 724
UVM_INFO @ 10034155369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 103187815244380618320726273831200736191858802179041068818173584548473131534444 915
UVM_INFO @ 5773019631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---