Simulation Results: aes/unmasked

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.19 %
  • code
  • 91.38 %
  • assert
  • 97.75 %
  • func
  • 63.43 %
  • block
  • 90.96 %
  • line
  • 93.22 %
  • branch
  • 83.54 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 100.945us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 69.484us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 67.793us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 57.431us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1367.146us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 287.020us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 89.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 57.431us 1 1 100.00
aes_csr_aliasing 3.000s 287.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 69.484us 1 1 100.00
aes_config_error 2.000s 186.139us 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 69.484us 1 1 100.00
aes_config_error 2.000s 186.139us 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 313.406us 1 1 100.00
aes_b2b 2.000s 90.258us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 69.484us 1 1 100.00
aes_config_error 2.000s 186.139us 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
aes_alert_reset 21.000s 10034.293us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 84.487us 1 1 100.00
aes_config_error 2.000s 186.139us 1 1 100.00
aes_alert_reset 21.000s 10034.293us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 120.187us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 310.493us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 526.034us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 21.000s 10034.293us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 313.406us 1 1 100.00
aes_sideload 2.000s 142.335us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 61.451us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 57.000s 10165.307us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 61.973us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 62.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 565.640us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 565.640us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 67.793us 1 1 100.00
aes_csr_rw 1.000s 57.431us 1 1 100.00
aes_csr_aliasing 3.000s 287.020us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.936us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 67.793us 1 1 100.00
aes_csr_rw 1.000s 57.431us 1 1 100.00
aes_csr_aliasing 3.000s 287.020us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 146.036us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 123.492us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 884.092us 1 1 100.00
aes_tl_intg_err 3.000s 335.204us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 335.204us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 21.000s 10034.293us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 69.484us 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
aes_alert_reset 21.000s 10034.293us 0 1 0.00
aes_core_fi 2.000s 62.694us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 61.973us 1 1 100.00
aes_config_error 2.000s 186.139us 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
aes_core_fi 2.000s 62.694us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.352us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 66.606us 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 313.406us 1 1 100.00
aes_sideload 2.000s 142.335us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.606us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.606us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 66.606us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 66.606us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 66.606us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 313.406us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 25.000s 10011.930us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
aes_ctr_fi 2.000s 58.379us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 25.000s 10011.930us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 25.000s 10011.930us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 58.379us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 25.000s 10011.930us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
aes_ctr_fi 2.000s 58.379us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 21.000s 10034.293us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
aes_ctr_fi 2.000s 58.379us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
aes_ctr_fi 2.000s 58.379us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 58.379us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 25.000s 10011.930us 0 1 0.00
aes_ghash_fi 2.000s 62.920us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 25.000s 10011.930us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 135.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 4195.917us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 45666905879945966110008171101147745640413666549049196266126862105705750704506 3206
UVM_INFO @ 10034292982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 33107570009663704781894349582808305854740421204739045191065949886314301274387 9373
UVM_INFO @ 10165307083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 81942127502426553378676960709230799262491947698269913681394818348977910266824 745
UVM_INFO @ 10011930031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
aes_control_fi 26491373609472491833166481221818451215089051128979239056902849530510880312081 None
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 31566213685082754569660614801292737116620392714684954975504606538419502209618 329
UVM_INFO @ 4195916718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---