Simulation Results: alert_handler

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.77 %
  • code
  • 91.88 %
  • assert
  • 98.20 %
  • func
  • 76.22 %
  • line
  • 99.73 %
  • branch
  • 97.80 %
  • cond
  • 91.17 %
  • toggle
  • 93.26 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 16.140s 779.135us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.290s 156.784us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.380s 402.784us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 159.400s 17931.121us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 197.740s 15967.212us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 9.820s 663.838us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.380s 402.784us 1 1 100.00
alert_handler_csr_aliasing 197.740s 15967.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 115.540s 5051.119us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 18.410s 287.609us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 638.250s 7780.912us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 40.960s 1066.232us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 16.140s 779.135us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 18.910s 304.980us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 31.320s 1221.347us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 6.310s 137.030us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1239.290s 32228.470us 1 1 100.00
alert_handler_lpg_stub_clk 1346.750s 106310.376us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 99.160s 4539.014us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 22.020s 614.375us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.210s 35.420us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.650s 6.842us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 12.250s 116.671us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 12.250s 116.671us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.290s 156.784us 1 1 100.00
alert_handler_csr_rw 7.380s 402.784us 1 1 100.00
alert_handler_csr_aliasing 197.740s 15967.212us 1 1 100.00
alert_handler_same_csr_outstanding 18.920s 262.596us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.290s 156.784us 1 1 100.00
alert_handler_csr_rw 7.380s 402.784us 1 1 100.00
alert_handler_csr_aliasing 197.740s 15967.212us 1 1 100.00
alert_handler_same_csr_outstanding 18.920s 262.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 108.610s 2117.445us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 108.610s 2117.445us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 108.610s 2117.445us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 108.610s 2117.445us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 478.340s 18174.154us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
alert_handler_tl_intg_err 1.870s 62.601us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 1.870s 62.601us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 108.610s 2117.445us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 16.140s 779.135us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 16.140s 779.135us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 16.140s 779.135us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 16.140s 779.135us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 40.960s 1066.232us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1239.290s 32228.470us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 40.960s 1066.232us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 638.250s 7780.912us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 638.250s 7780.912us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.860s 3214.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 131.030s 8980.918us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.
alert_handler_ping_timeout 75893112629538887396135832836230000907621351855066258927966254391274504654285 80
UVM_INFO @ 137030000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---