Simulation Results: clkmgr

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.72 %
  • code
  • 69.68 %
  • assert
  • 91.12 %
  • func
  • 72.36 %
  • line
  • 82.27 %
  • branch
  • 87.42 %
  • cond
  • 79.19 %
  • toggle
  • 99.53 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
69.23%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.950s 45.766us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.840s 17.912us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.970s 349.328us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.120s 39.715us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.320s 58.910us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
clkmgr_csr_aliasing 1.120s 39.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.810s 17.663us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 3.680s 369.413us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.740s 19.117us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.950s 45.766us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.720s 9.150us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.730s 5.712us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.720s 9.150us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.640s 8.528us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 22.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.420s 141.028us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.420s 141.028us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.840s 17.912us 1 1 100.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
clkmgr_csr_aliasing 1.120s 39.715us 1 1 100.00
clkmgr_same_csr_outstanding 1.190s 43.932us 1 1 100.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.840s 17.912us 1 1 100.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
clkmgr_csr_aliasing 1.120s 39.715us 1 1 100.00
clkmgr_same_csr_outstanding 1.190s 43.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.780s 296.354us 1 1 100.00
clkmgr_tl_intg_err 0.640s 2.737us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.450s 57.113us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.450s 57.113us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.450s 57.113us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.450s 57.113us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.660s 9.169us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.640s 2.737us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.720s 9.150us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.730s 5.712us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.450s 57.113us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.300s 66.957us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.780s 296.354us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.710s 3.657us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.780s 296.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.650s 8.399us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.270s 78.885us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 4070849660216094808789476345085769954348109928069717338834689086992585058322 76
UVM_INFO @ 9149966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 83287734561304716955749874718255642745141780711785769736840126808143349819350 78
UVM_INFO @ 78884895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 15179162381767268202945695079265129588922246560673642523519309661734243833147 76
UVM_INFO @ 8527594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 19774181248722633830011766962386113043661356728143398216067827711290629589088 78
UVM_INFO @ 5711890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 41488959536516050903672258499585865342145706782007528295195148470174092385117 74
UVM_INFO @ 8399467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 108559110566405183521494257330988559897757401048858638057777267327764048109404 75
UVM_INFO @ 9169227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 13377160845202719711411666686249907264169870556116911663919069502362960541676 75
UVM_INFO @ 2737476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 86346521555456885224134963059092726928175799206076479339069854259040643488442 75
UVM_INFO @ 3656515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 106095756643838472573175464436287896660715717621346125089419321624275698827197 75
UVM_INFO @ 349328386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---